[llvm] r351817 - [X86][BtVer2] SSE2 vector shifts has local forwarding disabled
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 22 05:27:18 PST 2019
Author: rksimon
Date: Tue Jan 22 05:27:18 2019
New Revision: 351817
URL: http://llvm.org/viewvc/llvm-project?rev=351817&view=rev
Log:
[X86][BtVer2] SSE2 vector shifts has local forwarding disabled
Similar to horizontal ops on D56777, the sse2 (but not mmx) bit shift ops has local forwarding disabled, adding +1cy to the use latency for the result.
Differential Revision: https://reviews.llvm.org/D57026
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=351817&r1=351816&r2=351817&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Tue Jan 22 05:27:18 2019
@@ -487,11 +487,11 @@ defm : JWriteResFpuPair<WriteVecALUX,
defm : X86WriteResPairUnsupported<WriteVecALUY>;
defm : X86WriteResPairUnsupported<WriteVecALUZ>;
defm : JWriteResFpuPair<WriteVecShift, [JFPU01, JVALU], 1>;
-defm : JWriteResFpuPair<WriteVecShiftX, [JFPU01, JVALU], 1>;
+defm : JWriteResFpuPair<WriteVecShiftX, [JFPU01, JVALU], 2>; // +1cy latency.
defm : X86WriteResPairUnsupported<WriteVecShiftY>;
defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
defm : JWriteResFpuPair<WriteVecShiftImm, [JFPU01, JVALU], 1>;
-defm : JWriteResFpuPair<WriteVecShiftImmX,[JFPU01, JVALU], 1>;
+defm : JWriteResFpuPair<WriteVecShiftImmX,[JFPU01, JVALU], 2>; // +1cy latency.
defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;
defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
defm : X86WriteResPairUnsupported<WriteVarVecShift>;
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=351817&r1=351816&r2=351817&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Tue Jan 22 05:27:18 2019
@@ -12146,16 +12146,16 @@ define <4 x i32> @test_pslld(<4 x i32> %
;
; BTVER2-SSE-LABEL: test_pslld:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: pslld %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: pslld (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: pslld $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: pslld %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: pslld (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: pslld $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_pslld:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_pslld:
@@ -12393,16 +12393,16 @@ define <2 x i64> @test_psllq(<2 x i64> %
;
; BTVER2-SSE-LABEL: test_psllq:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psllq %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psllq (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: psllq $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: psllq %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psllq (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: psllq $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psllq:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psllq:
@@ -12535,16 +12535,16 @@ define <8 x i16> @test_psllw(<8 x i16> %
;
; BTVER2-SSE-LABEL: test_psllw:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psllw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psllw (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: psllw $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: psllw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psllw (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: psllw $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psllw:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psllw:
@@ -12677,16 +12677,16 @@ define <4 x i32> @test_psrad(<4 x i32> %
;
; BTVER2-SSE-LABEL: test_psrad:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psrad %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psrad (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: psrad $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: psrad %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psrad (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: psrad $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psrad:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psrad:
@@ -12819,16 +12819,16 @@ define <8 x i16> @test_psraw(<8 x i16> %
;
; BTVER2-SSE-LABEL: test_psraw:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psraw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psraw (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: psraw $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: psraw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psraw (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: psraw $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psraw:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psraw:
@@ -12961,16 +12961,16 @@ define <4 x i32> @test_psrld(<4 x i32> %
;
; BTVER2-SSE-LABEL: test_psrld:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psrld %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psrld (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: psrld $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: psrld %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psrld (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: psrld $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psrld:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psrld:
@@ -13208,16 +13208,16 @@ define <2 x i64> @test_psrlq(<2 x i64> %
;
; BTVER2-SSE-LABEL: test_psrlq:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psrlq %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psrlq (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: psrlq $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: psrlq %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psrlq (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: psrlq $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psrlq:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psrlq:
@@ -13350,16 +13350,16 @@ define <8 x i16> @test_psrlw(<8 x i16> %
;
; BTVER2-SSE-LABEL: test_psrlw:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psrlw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psrlw (%rdi), %xmm0 # sched: [6:1.00]
-; BTVER2-SSE-NEXT: psrlw $2, %xmm0 # sched: [1:0.50]
+; BTVER2-SSE-NEXT: psrlw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psrlw (%rdi), %xmm0 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: psrlw $2, %xmm0 # sched: [2:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psrlw:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; BTVER2-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [2:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psrlw:
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s?rev=351817&r1=351816&r2=351817&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s Tue Jan 22 05:27:18 2019
@@ -1562,32 +1562,32 @@ vzeroupper
# CHECK-NEXT: 1 6 1.00 * vpsignd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsignw %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 1 6 1.00 * vpsignw (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpslld $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpslld %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpslld (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsllq $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsllq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsllq (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsllw $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsllw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsllw (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrad $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrad %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsrad (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsraw $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsraw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsraw (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrld $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrld %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsrld (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrlq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsrlq (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %xmm0, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsrlw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsrlw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsubb %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 1 6 1.00 * vpsubb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsubd %xmm0, %xmm1, %xmm2
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s?rev=351817&r1=351816&r2=351817&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s Tue Jan 22 05:27:18 2019
@@ -586,32 +586,32 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: 1 6 1.00 * pshufhw $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
# CHECK-NEXT: 1 6 1.00 * pshuflw $1, (%rax), %xmm2
-# CHECK-NEXT: 1 1 0.50 pslld $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 pslld %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * pslld (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 pslld $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 pslld %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * pslld (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psllq $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psllq %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * psllq (%rax), %xmm2
-# CHECK-NEXT: 1 1 0.50 psllw $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psllw %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * psllw (%rax), %xmm2
-# CHECK-NEXT: 1 1 0.50 psrad $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psrad %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * psrad (%rax), %xmm2
-# CHECK-NEXT: 1 1 0.50 psraw $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psraw %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * psraw (%rax), %xmm2
-# CHECK-NEXT: 1 1 0.50 psrld $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psrld %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * psrld (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 psllq $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 psllq %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * psllq (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 psllw $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 psllw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * psllw (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 psrad $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 psrad %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * psrad (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 psraw $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 psraw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * psraw (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 psrld $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 psrld %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * psrld (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psrlq $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psrlq %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * psrlq (%rax), %xmm2
-# CHECK-NEXT: 1 1 0.50 psrlw $1, %xmm2
-# CHECK-NEXT: 1 1 0.50 psrlw %xmm0, %xmm2
-# CHECK-NEXT: 1 6 1.00 * psrlw (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 psrlq $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 psrlq %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * psrlq (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 psrlw $1, %xmm2
+# CHECK-NEXT: 1 2 0.50 psrlw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 1.00 * psrlw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psubb %xmm0, %xmm2
# CHECK-NEXT: 1 6 1.00 * psubb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psubd %xmm0, %xmm2
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