[llvm] r351796 - Revert r351778: IR: Add fp operations to atomicrmw
Chandler Carruth via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 22 02:29:58 PST 2019
Author: chandlerc
Date: Tue Jan 22 02:29:58 2019
New Revision: 351796
URL: http://llvm.org/viewvc/llvm-project?rev=351796&view=rev
Log:
Revert r351778: IR: Add fp operations to atomicrmw
This broke the RISCV build, and even with that fixed, one of the RISCV
tests behaves surprisingly differently with asserts than without,
leaving there no clear test pattern to use. Generally it seems bad for
hte IR to differ substantially due to asserts (as in, an alloca is used
with asserts that isn't needed without!) and nothing I did simply would
fix it so I'm reverting back to green.
This also required reverting the RISCV build fix in r351782.
Removed:
llvm/trunk/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll
llvm/trunk/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll
llvm/trunk/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
llvm/trunk/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
llvm/trunk/test/Transforms/AtomicExpand/Hexagon/
llvm/trunk/test/Transforms/AtomicExpand/Mips/
llvm/trunk/test/Transforms/AtomicExpand/RISCV/
Modified:
llvm/trunk/docs/LangRef.rst
llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
llvm/trunk/include/llvm/CodeGen/TargetLowering.h
llvm/trunk/include/llvm/IR/Instructions.h
llvm/trunk/lib/AsmParser/LLParser.cpp
llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp
llvm/trunk/lib/IR/Instructions.cpp
llvm/trunk/lib/IR/Verifier.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/test/Assembler/atomic.ll
llvm/trunk/test/Bitcode/compatibility.ll
Modified: llvm/trunk/docs/LangRef.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.rst (original)
+++ llvm/trunk/docs/LangRef.rst Tue Jan 22 02:29:58 2019
@@ -8667,18 +8667,15 @@ operation. The operation must be one of
- min
- umax
- umin
-- fadd
-- fsub
For most of these operations, the type of '<value>' must be an integer
type whose bit width is a power of two greater than or equal to eight
and less than or equal to a target-specific size limit. For xchg, this
may also be a floating point type with the same size constraints as
-integers. For fadd/fsub, this must be a floating point type. The
-type of the '``<pointer>``' operand must be a pointer to that type. If
-the ``atomicrmw`` is marked as ``volatile``, then the optimizer is not
-allowed to modify the number or order of execution of this
-``atomicrmw`` with other :ref:`volatile operations <volatile>`.
+integers. The type of the '``<pointer>``' operand must be a pointer to
+that type. If the ``atomicrmw`` is marked as ``volatile``, then the
+optimizer is not allowed to modify the number or order of execution of
+this ``atomicrmw`` with other :ref:`volatile operations <volatile>`.
A ``atomicrmw`` instruction can also take an optional
":ref:`syncscope <syncscope>`" argument.
@@ -8704,8 +8701,6 @@ operation argument:
comparison)
- umin: ``*ptr = *ptr < val ? *ptr : val`` (using an unsigned
comparison)
-- fadd: ``*ptr = *ptr + val`` (using floating point arithmetic)
-- fsub: ``*ptr = *ptr - val`` (using floating point arithmetic)
Example:
""""""""
Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Tue Jan 22 02:29:58 2019
@@ -406,9 +406,7 @@ enum RMWOperations {
RMW_MAX = 7,
RMW_MIN = 8,
RMW_UMAX = 9,
- RMW_UMIN = 10,
- RMW_FADD = 11,
- RMW_FSUB = 12
+ RMW_UMIN = 10
};
/// OverflowingBinaryOperatorOptionalFlags - Flags for serializing
Modified: llvm/trunk/include/llvm/CodeGen/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLowering.h?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetLowering.h Tue Jan 22 02:29:58 2019
@@ -1715,9 +1715,8 @@ public:
/// Returns how the IR-level AtomicExpand pass should expand the given
/// AtomicRMW, if at all. Default is to never expand.
- virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
- return RMW->isFloatingPointOperation() ?
- AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
+ virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
+ return AtomicExpansionKind::None;
}
/// On some platforms, an AtomicRMW that never actually modifies the value
Modified: llvm/trunk/include/llvm/IR/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/Instructions.h?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/Instructions.h (original)
+++ llvm/trunk/include/llvm/IR/Instructions.h Tue Jan 22 02:29:58 2019
@@ -724,14 +724,8 @@ public:
/// *p = old <unsigned v ? old : v
UMin,
- /// *p = old + v
- FAdd,
-
- /// *p = old - v
- FSub,
-
FIRST_BINOP = Xchg,
- LAST_BINOP = FSub,
+ LAST_BINOP = UMin,
BAD_BINOP
};
@@ -753,16 +747,6 @@ public:
static StringRef getOperationName(BinOp Op);
- static bool isFPOperation(BinOp Op) {
- switch (Op) {
- case AtomicRMWInst::FAdd:
- case AtomicRMWInst::FSub:
- return true;
- default:
- return false;
- }
- }
-
void setOperation(BinOp Operation) {
unsigned short SubclassData = getSubclassDataFromInstruction();
setInstructionSubclassData((SubclassData & 31) |
@@ -820,10 +804,6 @@ public:
return getPointerOperand()->getType()->getPointerAddressSpace();
}
- bool isFloatingPointOperation() const {
- return isFPOperation(getOperation());
- }
-
// Methods for support type inquiry through isa, cast, and dyn_cast:
static bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::AtomicRMW;
Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Tue Jan 22 02:29:58 2019
@@ -6815,7 +6815,6 @@ int LLParser::ParseAtomicRMW(Instruction
AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
SyncScope::ID SSID = SyncScope::System;
bool isVolatile = false;
- bool IsFP = false;
AtomicRMWInst::BinOp Operation;
if (EatIfPresent(lltok::kw_volatile))
@@ -6834,14 +6833,6 @@ int LLParser::ParseAtomicRMW(Instruction
case lltok::kw_min: Operation = AtomicRMWInst::Min; break;
case lltok::kw_umax: Operation = AtomicRMWInst::UMax; break;
case lltok::kw_umin: Operation = AtomicRMWInst::UMin; break;
- case lltok::kw_fadd:
- Operation = AtomicRMWInst::FAdd;
- IsFP = true;
- break;
- case lltok::kw_fsub:
- Operation = AtomicRMWInst::FSub;
- IsFP = true;
- break;
}
Lex.Lex(); // Eat the operation.
@@ -6858,25 +6849,18 @@ int LLParser::ParseAtomicRMW(Instruction
if (cast<PointerType>(Ptr->getType())->getElementType() != Val->getType())
return Error(ValLoc, "atomicrmw value and pointer type do not match");
- if (Operation == AtomicRMWInst::Xchg) {
- if (!Val->getType()->isIntegerTy() &&
- !Val->getType()->isFloatingPointTy()) {
- return Error(ValLoc, "atomicrmw " +
- AtomicRMWInst::getOperationName(Operation) +
- " operand must be an integer or floating point type");
- }
- } else if (IsFP) {
- if (!Val->getType()->isFloatingPointTy()) {
- return Error(ValLoc, "atomicrmw " +
- AtomicRMWInst::getOperationName(Operation) +
- " operand must be a floating point type");
- }
- } else {
- if (!Val->getType()->isIntegerTy()) {
- return Error(ValLoc, "atomicrmw " +
- AtomicRMWInst::getOperationName(Operation) +
- " operand must be an integer");
- }
+ if (Operation != AtomicRMWInst::Xchg && !Val->getType()->isIntegerTy()) {
+ return Error(ValLoc, "atomicrmw " +
+ AtomicRMWInst::getOperationName(Operation) +
+ " operand must be an integer");
+ }
+
+ if (Operation == AtomicRMWInst::Xchg &&
+ !Val->getType()->isIntegerTy() &&
+ !Val->getType()->isFloatingPointTy()) {
+ return Error(ValLoc, "atomicrmw " +
+ AtomicRMWInst::getOperationName(Operation) +
+ " operand must be an integer or floating point type");
}
unsigned Size = Val->getType()->getPrimitiveSizeInBits();
Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Tue Jan 22 02:29:58 2019
@@ -1034,8 +1034,6 @@ static AtomicRMWInst::BinOp getDecodedRM
case bitc::RMW_MIN: return AtomicRMWInst::Min;
case bitc::RMW_UMAX: return AtomicRMWInst::UMax;
case bitc::RMW_UMIN: return AtomicRMWInst::UMin;
- case bitc::RMW_FADD: return AtomicRMWInst::FAdd;
- case bitc::RMW_FSUB: return AtomicRMWInst::FSub;
}
}
Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Tue Jan 22 02:29:58 2019
@@ -559,8 +559,6 @@ static unsigned getEncodedRMWOperation(A
case AtomicRMWInst::Min: return bitc::RMW_MIN;
case AtomicRMWInst::UMax: return bitc::RMW_UMAX;
case AtomicRMWInst::UMin: return bitc::RMW_UMIN;
- case AtomicRMWInst::FAdd: return bitc::RMW_FADD;
- case AtomicRMWInst::FSub: return bitc::RMW_FSUB;
}
}
Modified: llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp Tue Jan 22 02:29:58 2019
@@ -549,10 +549,6 @@ static Value *performAtomicOp(AtomicRMWI
case AtomicRMWInst::UMin:
NewVal = Builder.CreateICmpULE(Loaded, Inc);
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
- case AtomicRMWInst::FAdd:
- return Builder.CreateFAdd(Loaded, Inc, "new");
- case AtomicRMWInst::FSub:
- return Builder.CreateFSub(Loaded, Inc, "new");
default:
llvm_unreachable("Unknown atomic op");
}
@@ -1551,8 +1547,6 @@ static ArrayRef<RTLIB::Libcall> GetRMWLi
case AtomicRMWInst::Min:
case AtomicRMWInst::UMax:
case AtomicRMWInst::UMin:
- case AtomicRMWInst::FAdd:
- case AtomicRMWInst::FSub:
// No atomic libcalls are available for max/min/umax/umin.
return {};
}
Modified: llvm/trunk/lib/IR/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Instructions.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/IR/Instructions.cpp (original)
+++ llvm/trunk/lib/IR/Instructions.cpp Tue Jan 22 02:29:58 2019
@@ -1407,10 +1407,6 @@ StringRef AtomicRMWInst::getOperationNam
return "umax";
case AtomicRMWInst::UMin:
return "umin";
- case AtomicRMWInst::FAdd:
- return "fadd";
- case AtomicRMWInst::FSub:
- return "fsub";
case AtomicRMWInst::BAD_BINOP:
return "<invalid operation>";
}
Modified: llvm/trunk/lib/IR/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Verifier.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/IR/Verifier.cpp (original)
+++ llvm/trunk/lib/IR/Verifier.cpp Tue Jan 22 02:29:58 2019
@@ -3435,11 +3435,6 @@ void Verifier::visitAtomicRMWInst(Atomic
AtomicRMWInst::getOperationName(Op) +
" operand must have integer or floating point type!",
&RMWI, ElTy);
- } else if (AtomicRMWInst::isFPOperation(Op)) {
- Assert(ElTy->isFloatingPointTy(), "atomicrmw " +
- AtomicRMWInst::getOperationName(Op) +
- " operand must have floating point type!",
- &RMWI, ElTy);
} else {
Assert(ElTy->isIntegerTy(), "atomicrmw " +
AtomicRMWInst::getOperationName(Op) +
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Jan 22 02:29:58 2019
@@ -11600,9 +11600,6 @@ AArch64TargetLowering::shouldExpandAtomi
// For the real atomic operations, we have ldxr/stxr up to 128 bits,
TargetLowering::AtomicExpansionKind
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
- if (AI->isFloatingPointOperation())
- return AtomicExpansionKind::CmpXChg;
-
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
if (Size > 128) return AtomicExpansionKind::None;
// Nand not supported in LSE.
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jan 22 02:29:58 2019
@@ -14645,9 +14645,6 @@ ARMTargetLowering::shouldExpandAtomicLoa
// and up to 64 bits on the non-M profiles
TargetLowering::AtomicExpansionKind
ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
- if (AI->isFloatingPointOperation())
- return AtomicExpansionKind::CmpXChg;
-
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
bool hasAtomicRMW = !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps();
return (Size <= (Subtarget->isMClass() ? 32U : 64U) && hasAtomicRMW)
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue Jan 22 02:29:58 2019
@@ -3110,21 +3110,13 @@ Value *HexagonTargetLowering::emitLoadLi
AtomicOrdering Ord) const {
BasicBlock *BB = Builder.GetInsertBlock();
Module *M = BB->getParent()->getParent();
- auto PT = cast<PointerType>(Addr->getType());
- Type *Ty = PT->getElementType();
+ Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
unsigned SZ = Ty->getPrimitiveSizeInBits();
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
: Intrinsic::hexagon_L4_loadd_locked;
-
- PointerType *NewPtrTy
- = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
- Addr = Builder.CreateBitCast(Addr, NewPtrTy);
-
Value *Fn = Intrinsic::getDeclaration(M, IntID);
- Value *Call = Builder.CreateCall(Fn, Addr, "larx");
-
- return Builder.CreateBitCast(Call, Ty);
+ return Builder.CreateCall(Fn, Addr, "larx");
}
/// Perform a store-conditional operation to Addr. Return the status of the
@@ -3135,17 +3127,10 @@ Value *HexagonTargetLowering::emitStoreC
Module *M = BB->getParent()->getParent();
Type *Ty = Val->getType();
unsigned SZ = Ty->getPrimitiveSizeInBits();
-
- Type *CastTy = Builder.getIntNTy(SZ);
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
: Intrinsic::hexagon_S4_stored_locked;
Value *Fn = Intrinsic::getDeclaration(M, IntID);
-
- unsigned AS = Addr->getType()->getPointerAddressSpace();
- Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
- Val = Builder.CreateBitCast(Val, CastTy);
-
Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Tue Jan 22 02:29:58 2019
@@ -1720,12 +1720,6 @@ Instruction *RISCVTargetLowering::emitTr
TargetLowering::AtomicExpansionKind
RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
- // atomicrmw {fadd,fsub} must be expanded to use compare-exchange, as
- // floating point operations can't be used in an lr/sc sequence without
- // brekaing the forward-progress guarantee.
- if (AI->isFloatingPointOperation())
- return AtomicExpansionKind::CmpXChg;
-
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
if (Size == 8 || Size == 16)
return AtomicExpansionKind::MaskedIntrinsic;
Modified: llvm/trunk/test/Assembler/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/atomic.ll?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/test/Assembler/atomic.ll (original)
+++ llvm/trunk/test/Assembler/atomic.ll Tue Jan 22 02:29:58 2019
@@ -39,13 +39,3 @@ define void @f(i32* %x) {
fence syncscope("device") seq_cst
ret void
}
-
-define void @fp_atomics(float* %x) {
- ; CHECK: atomicrmw fadd float* %x, float 1.000000e+00 seq_cst
- atomicrmw fadd float* %x, float 1.0 seq_cst
-
- ; CHECK: atomicrmw volatile fadd float* %x, float 1.000000e+00 seq_cst
- atomicrmw volatile fadd float* %x, float 1.0 seq_cst
-
- ret void
-}
Removed: llvm/trunk/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll?rev=351795&view=auto
==============================================================================
--- llvm/trunk/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll (original)
+++ llvm/trunk/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll (removed)
@@ -1,7 +0,0 @@
-; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s
-
-; CHECK: error: atomicrmw fadd operand must be a floating point type
-define void @f(i32* %ptr) {
- atomicrmw fadd i32* %ptr, i32 2 seq_cst
- ret void
-}
Removed: llvm/trunk/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll?rev=351795&view=auto
==============================================================================
--- llvm/trunk/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll (original)
+++ llvm/trunk/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll (removed)
@@ -1,7 +0,0 @@
-; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s
-
-; CHECK: error: atomicrmw fsub operand must be a floating point type
-define void @f(i32* %ptr) {
- atomicrmw fsub i32* %ptr, i32 2 seq_cst
- ret void
-}
Modified: llvm/trunk/test/Bitcode/compatibility.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/compatibility.ll?rev=351796&r1=351795&r2=351796&view=diff
==============================================================================
--- llvm/trunk/test/Bitcode/compatibility.ll (original)
+++ llvm/trunk/test/Bitcode/compatibility.ll Tue Jan 22 02:29:58 2019
@@ -764,13 +764,6 @@ define void @atomics(i32* %word) {
define void @fp_atomics(float* %word) {
; CHECK: %atomicrmw.xchg = atomicrmw xchg float* %word, float 1.000000e+00 monotonic
%atomicrmw.xchg = atomicrmw xchg float* %word, float 1.0 monotonic
-
-; CHECK: %atomicrmw.fadd = atomicrmw fadd float* %word, float 1.000000e+00 monotonic
- %atomicrmw.fadd = atomicrmw fadd float* %word, float 1.0 monotonic
-
-; CHECK: %atomicrmw.fsub = atomicrmw fsub float* %word, float 1.000000e+00 monotonic
- %atomicrmw.fsub = atomicrmw fsub float* %word, float 1.0 monotonic
-
ret void
}
Removed: llvm/trunk/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll?rev=351795&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll (original)
+++ llvm/trunk/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll (removed)
@@ -1,47 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=aarch64-linux-gnu -atomic-expand %s | FileCheck %s
-
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
- ret float %res
-}
-
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
- ret float %res
-}
-
Removed: llvm/trunk/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll?rev=351795&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll (original)
+++ llvm/trunk/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll (removed)
@@ -1,51 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=armv7-apple-ios7.0 -atomic-expand %s | FileCheck %s
-
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
- ret float %res
-}
-
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
- ret float %res
-}
-
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