[PATCH] D55163: AMDGPU: Add optimization patterns to combine fp32->fp16 conversions

Mon Jan 21 15:01:00 PST 2019

arsenm added inline comments.

================
Comment at: lib/Target/AMDGPU/SIInstructions.td:1597

+let SubtargetPredicate = isGCN in {
+
----------------
pendingchaos wrote:
> arsenm wrote:
> > Should use isVI, or maybe these should be distinguished by GCN3Encoding? Needs a comment for why these are separated 
> Since all GCN versions support the VOP3a form, shouldn't it use isGCN (to combine the modifiers into the instruction on SI/CI)?
> 
> The VOP2 form is only supported on SI/CI, so isSICI is used. IIRC VOP2 ended up being used when no modifiers could be folded.
isGCN is obsolete and should be removed anywhere it's used.

Since we try to shrink instructions later, we only want to select the _e64 version when possible

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55163/new/

https://reviews.llvm.org/D55163