[PATCH] D56281: [DAGCombiner] reduce buildvec of zexted extracted element to shuffle

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

Hello. I am investigating a crash and this assertion failure on AArch64:

  lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1548: llvm::SDValue llvm::SelectionDAG::getVectorShuffle(llvm::EVT, const llvm::SDLoc&, llvm::SDValue, llvm::SDValue, llvm::ArrayRef<int>): Assertion `VT.getVectorNumElements() == Mask.size() && "Must have the same number of vector elements as mask elements!"' failed.

Bisecting is blaming this commit. I've only just started debugging this (and it is hitting this new function), but just wanted to share this in case you have some ideas and thoughts on this. This is my reproducer:

  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64-unknown-linux-gnu"
  
  @a = common dso_local local_unnamed_addr global <4 x i16> zeroinitializer, align 8
  @b = common dso_local local_unnamed_addr global i32 0, align 4
  
  ; Function Attrs: nounwind
  define dso_local i32 @vqmovns_s32() local_unnamed_addr {
  entry:
    %0 = load <4 x i16>, <4 x i16>* @a, align 8
    %1 = extractelement <4 x i16> %0, i32 2
    %vgetq_lane = zext i16 %1 to i32
    %2 = insertelement <4 x i32> undef, i32 %vgetq_lane, i64 0
    %vqmovns_s32 = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %2)
    %3 = extractelement <4 x i16> %vqmovns_s32, i64 0
    %conv = sext i16 %3 to i32
    store i32 %conv, i32* @b, align 4
    ret i32 undef
  }
  
  ; Function Attrs: nounwind readnone
  declare <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32>)


Repository:
  rL LLVM

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