[PATCH] D56922: [X86][BtVer2] Update the WriteLoad latency.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:273
 // Load/store MXCSR.
 // FIXME: These are copy and pasted from WriteLoad/Store.
+def : WriteRes<WriteLDMXCSR, [JLAGU]> { let Latency = 3; }
----------------
Can we remove this FIXME?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56922/new/

https://reviews.llvm.org/D56922