[PATCH] D56534: [Verifier] Add verification of unaligned atomic load/store

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D56534#1354624 <https://reviews.llvm.org/D56534#1354624>, @efriedma wrote:

> See http://reviews.llvm.org/D18200


Thanks for the pointer.  I've read through the documentation introduced in that patch, and I'm still left wondering.

If we have say a 16 byte aligned CAS and a 16 byte *unaligned* CAS operation on x86-64, I don't see how we can implement them via the atomic library contract.  Specifically, the aligned 16 byte CAS can be represented via a CMPXCHG16b.  Given this, we're required to find a locked implementation for the *unaligned* case, and the SPEC for CMPXCHG16b explicitly states that a fault is generated if an unaligned address is used.  Given that, we have no choice but to use a lock pattern.  However, that means we can have two overlapping 16 byte accesses (one aligned, one not) and be unable to provide a correct implementation.

To prevent confusion, this problem doesn't exist for 8 bytes or smaller, due to the availability of the larger CAS.  It's only 16 byte accesses which have this problem.

I think the strongest guarantee we can provide is a target defined maximum size of atomics which differs based on alignment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56534/new/

https://reviews.llvm.org/D56534