[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added inline comments.


================
Comment at: lib/Target/X86/X86TargetTransformInfo.cpp:150
 
+unsigned X86TTIImpl::getMinVectorRegisterBitWidth() const {
+  return 64;
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anton-afanasyev wrote:
> ABataev wrote:
> > anton-afanasyev wrote:
> > > RKSimon wrote:
> > > > anton-afanasyev wrote:
> > > > > RKSimon wrote:
> > > > > > Can we add a IsFloat bool argument here?
> > > > > That is not possible: at this stage we can only operate by vector register width notion regardless of the scalars type. And what is the cause we can need it?
> > > > Don't refer to MMX - its gives the wrong impression that we actually generate code for it (all we ever do is emit intrinsic code).
> > > Ok, I'm to remove this from comment.
> > Still refers to MMX
> Do you mean reference in comment? Removed.
Yes, it was about the comment. Still, the comment does not match the function. It says about 128-bit operations but returns 64 as a result.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082