[PATCH] D56264: [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.


================
Comment at: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp:554
+  }
+  case ISD::ANY_EXTEND: {
+    // If any-extending an i32 variable-length shift to i64, then instead
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I've raised https://bugs.llvm.org/show_bug.cgi?id=40333 because this interacts badly with `TargetLowering::SimplifyDemandedBits`. This newly created `SIGN_EXTEND` is turned back into an `ANY_EXTEND` when it is used by an `(AND x, 255)`

Kind regards,


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56264/new/

https://reviews.llvm.org/D56264