[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev marked 3 inline comments as done.
anton-afanasyev added inline comments.


================
Comment at: lib/Target/X86/X86TargetTransformInfo.cpp:150-154
+// MMX 64-bit registers and horizontal 128-bit operations.
+// This also allows vectorizer to use partial vector operations.
+unsigned X86TTIImpl::getMinVectorRegisterBitWidth() const {
+  return 64;
+}
----------------
lebedev.ri wrote:
> anton-afanasyev wrote:
> > lebedev.ri wrote:
> > > I lack context, but will this also handle e.g. `_mm_hadd_epi16()` ?
> > Yes, phaddw is also handled.
> Then i don't understand the function name. (yes, i understand that it is a pre-existing hook)
> `_mm_hadd_epi16()` operates on `i16`, how come `64` is the right pick here?
64 is the size of whole vector with 16-bit elements packed in it. Here is a piece of manual:

```
PHADDW (with 64-bit operands):
mm1[15-0] = mm1[31-16] + mm1[15-0];
mm1[31-16] = mm1[63-48] + mm1[47-32];
mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];
mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082