[PATCH] D56772: [MIR] Add simple PRE pass to MachineCSE

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev created this revision.
anton-afanasyev added reviewers: RKSimon, MatzeB, spatel, craig.topper.
Herald added subscribers: llvm-commits, atanasyan, jrtc27, sdardis.

  This is the second part of the commit fixing PR38917 (hoisting
  partitially redundant machine instruction). Most of PRE (partitial
  redundancy elimination) and CSE work is done on LLVM IR, but some of
  redundancy arises during DAG legalization. Machine CSE is not enough
  to deal with it. This simple PRE implementation works a little bit
  intricately: it passes before CSE, looking for partitial redundancy
  and transforming it to fully redundancy, anticipating that the next
  CSE step will eliminate this created redundancy. If CSE doesn't
  eliminate this, than created instruction will remain dead and eliminated
  later by Remove Dead Machine Instructions pass.
  
  The third part of the commit is supposed to refactor MachineCSE,
  to make it more clear and to merge MachinePRE with MachineCSE,
  so one need no rely on further Remove Dead pass to clear instrs
  not eliminated by CSE.
  
  First step: https://reviews.llvm.org/D54839
  
  Fixes llvm.org/PR38917


Repository:
  rL LLVM

https://reviews.llvm.org/D56772

Files:
  lib/CodeGen/MachineCSE.cpp
  test/CodeGen/Mips/internalfunc.ll
  test/CodeGen/X86/avx2-masked-gather.ll
  test/CodeGen/X86/masked_gather.ll

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