[llvm] r351278 - [X86] Rename SHRUNKBLEND ISD node to BLENDV.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 15 16:20:30 PST 2019
Author: ctopper
Date: Tue Jan 15 16:20:30 2019
New Revision: 351278
URL: http://llvm.org/viewvc/llvm-project?rev=351278&view=rev
Log:
[X86] Rename SHRUNKBLEND ISD node to BLENDV.
That's really what it is. If we didn't use intrinsics for BLENDVPS/BLENDVPD/PBLENDVB all the way to isel, this is the node we would use.
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=351278&r1=351277&r2=351278&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Jan 15 16:20:30 2019
@@ -3381,8 +3381,8 @@ void X86DAGToDAGISel::Select(SDNode *Nod
}
break;
- case X86ISD::SHRUNKBLEND: {
- // SHRUNKBLEND selects like a regular VSELECT. Same with X86ISD::SELECT.
+ case X86ISD::BLENDV: {
+ // BLENDV selects like a regular VSELECT.
SDValue VSelect = CurDAG->getNode(
ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
Node->getOperand(1), Node->getOperand(2));
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=351278&r1=351277&r2=351278&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 15 16:20:30 2019
@@ -23582,7 +23582,7 @@ static SDValue LowerABS(SDValue Op, cons
SDValue Src = Op.getOperand(0);
SDValue Sub =
DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Src);
- return DAG.getNode(X86ISD::SHRUNKBLEND, DL, VT, Src, Sub, Src);
+ return DAG.getNode(X86ISD::BLENDV, DL, VT, Src, Sub, Src);
}
if (VT.is256BitVector() && !Subtarget.hasInt256()) {
@@ -27132,7 +27132,7 @@ const char *X86TargetLowering::getTarget
case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
case X86ISD::ANDNP: return "X86ISD::ANDNP";
case X86ISD::BLENDI: return "X86ISD::BLENDI";
- case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
+ case X86ISD::BLENDV: return "X86ISD::BLENDV";
case X86ISD::HADD: return "X86ISD::HADD";
case X86ISD::HSUB: return "X86ISD::HSUB";
case X86ISD::FHADD: return "X86ISD::FHADD";
@@ -33974,13 +33974,13 @@ static SDValue combineSelectOfTwoConstan
/// this node with one of the variable blend instructions, restructure the
/// condition so that blends can use the high (sign) bit of each element.
/// This function will also call SimplfiyDemandedBits on already created
-/// SHRUNKBLENDS to perform additional simplifications.
-static SDValue combineVSelectToShrunkBlend(SDNode *N, SelectionDAG &DAG,
+/// BLENDV to perform additional simplifications.
+static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
SDValue Cond = N->getOperand(0);
if ((N->getOpcode() != ISD::VSELECT &&
- N->getOpcode() != X86ISD::SHRUNKBLEND) ||
+ N->getOpcode() != X86ISD::BLENDV) ||
ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
return SDValue();
@@ -34023,7 +34023,7 @@ static SDValue combineVSelectToShrunkBle
for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end();
UI != UE; ++UI)
if ((UI->getOpcode() != ISD::VSELECT &&
- UI->getOpcode() != X86ISD::SHRUNKBLEND) ||
+ UI->getOpcode() != X86ISD::BLENDV) ||
UI.getOperandNo() != 0)
return SDValue();
@@ -34040,10 +34040,10 @@ static SDValue combineVSelectToShrunkBle
// optimizations as we messed with the actual expectation for the vector
// boolean values.
for (SDNode *U : Cond->uses()) {
- if (U->getOpcode() == X86ISD::SHRUNKBLEND)
+ if (U->getOpcode() == X86ISD::BLENDV)
continue;
- SDValue SB = DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(U), U->getValueType(0),
+ SDValue SB = DAG.getNode(X86ISD::BLENDV, SDLoc(U), U->getValueType(0),
Cond, U->getOperand(1), U->getOperand(2));
DAG.ReplaceAllUsesOfValueWith(SDValue(U, 0), SB);
DCI.AddToWorklist(U);
@@ -34062,7 +34062,7 @@ static SDValue combineSelect(SDNode *N,
SDValue RHS = N->getOperand(2);
// Try simplification again because we use this function to optimize
- // SHRUNKBLEND nodes that are not handled by the generic combiner.
+ // BLENDV nodes that are not handled by the generic combiner.
if (SDValue V = DAG.simplifySelect(Cond, LHS, RHS))
return V;
@@ -34429,7 +34429,7 @@ static SDValue combineSelect(SDNode *N,
if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DCI, Subtarget))
return V;
- if (SDValue V = combineVSelectToShrunkBlend(N, DAG, DCI, Subtarget))
+ if (SDValue V = combineVSelectToBLENDV(N, DAG, DCI, Subtarget))
return V;
// Custom action for SELECT MMX
@@ -41500,7 +41500,7 @@ SDValue X86TargetLowering::PerformDAGCom
return combineExtractSubvector(N, DAG, DCI, Subtarget);
case ISD::VSELECT:
case ISD::SELECT:
- case X86ISD::SHRUNKBLEND: return combineSelect(N, DAG, DCI, Subtarget);
+ case X86ISD::BLENDV: return combineSelect(N, DAG, DCI, Subtarget);
case ISD::BITCAST: return combineBitcast(N, DAG, DCI, Subtarget);
case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget);
case X86ISD::CMP: return combineCMP(N, DAG);
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=351278&r1=351277&r2=351278&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Jan 15 16:20:30 2019
@@ -203,8 +203,9 @@ namespace llvm {
/// Dynamic (non-constant condition) vector blend where only the sign bits
/// of the condition elements are used. This is used to enforce that the
- /// condition mask is not valid for generic VSELECT optimizations.
- SHRUNKBLEND,
+ /// condition mask is not valid for generic VSELECT optimizations. This
+ /// can also be used to implement the intrinsics.
+ BLENDV,
/// Combined add and sub on an FP vector.
ADDSUB,
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