[PATCH] D56715: X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: craig.topper, andreadb, RKSimon.

Noticed while looking at D56052 <https://reviews.llvm.org/D56052>.

  // The 'control' of BEXTR has the pattern of:
  // [15...8 bit][ 7...0 bit] location
  // [ bit count][     shift] name
  // I.e. 0b000000011'00000001 means  (x >> 0b1) & 0b11

I.e. we do not care about any of the bits aside from the low 16 bits.
So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed.

We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC),
so i'm guessing the same applies here.


Repository:
  rL LLVM

https://reviews.llvm.org/D56715

Files:
  lib/Target/X86/X86ISelDAGToDAG.cpp
  test/CodeGen/X86/extract-bits.ll
  test/CodeGen/X86/extract-lowbits.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D56715.181771.patch
Type: text/x-patch
Size: 19974 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190115/52ca33dd/attachment.bin>