[PATCH] D56714: [SLP] introduce control over arithmetic horizontal reduction

Fedor Sergeev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 15 03:10:37 PST 2019


fedor.sergeev created this revision.
fedor.sergeev added reviewers: RKSimon, spatel, ABataev.

Horizontal reduction on AND (relatively recent transformation
introduced by rL345037 <https://reviews.llvm.org/rL345037>) causes PR40310 miscompile.

Introducing -slp-vectorize-hor-arith boolean control to enable/disable
just horizontal reduction for arithmetic operations other than ADD/FADD.

Open question: true or false by default?


Repository:
  rL LLVM

https://reviews.llvm.org/D56714

Files:
  lib/Transforms/Vectorize/SLPVectorizer.cpp


Index: lib/Transforms/Vectorize/SLPVectorizer.cpp
===================================================================
--- lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -115,6 +115,10 @@
 ShouldVectorizeHor("slp-vectorize-hor", cl::init(true), cl::Hidden,
                    cl::desc("Attempt to vectorize horizontal reductions"));
 
+static cl::opt<bool>
+ShouldVectorizeHorArith("slp-vectorize-hor-arith", cl::init(false), cl::Hidden,
+                   cl::desc("Attempt to vectorize horizontal reductions for arithmetic operations other than add/fadd."));
+
 static cl::opt<bool> ShouldStartVectorizeHorAtStore(
     "slp-vectorize-hor-store", cl::init(false), cl::Hidden,
     cl::desc(
@@ -5131,9 +5135,10 @@
              // We currently only support add/mul/logical && min/max reductions.
              ((Kind == RK_Arithmetic &&
                (Opcode == Instruction::Add || Opcode == Instruction::FAdd ||
-                Opcode == Instruction::Mul || Opcode == Instruction::FMul ||
-                Opcode == Instruction::And || Opcode == Instruction::Or ||
-                Opcode == Instruction::Xor)) ||
+		(ShouldVectorizeHorArith &&
+		 (Opcode == Instruction::Mul || Opcode == Instruction::FMul ||
+		  Opcode == Instruction::And || Opcode == Instruction::Or ||
+		  Opcode == Instruction::Xor)))) ||
               ((Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) &&
                (Kind == RK_Min || Kind == RK_Max)) ||
               (Opcode == Instruction::ICmp &&


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