[PATCH] D56695: [X86] Add X86ISD::VSHLV and X86ISD::VSRLV nodes for psllv and psrlv

zhutianyang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 14 18:46:17 PST 2019


zhutianyang created this revision.
zhutianyang added a reviewer: craig.topper.
Herald added a subscriber: llvm-commits.

Previously we used ISD::SHL and ISD::SRL to represent these in SelectionDAG. ISD::SHL/SRL interpret an out of range shift amount as undefined behavior and will constant fold to undef. While the intrinsics are defined to return 0 for out of range shift amounts. A previous patch added a special node for VPSRAV to produce all sign bits.

This was previously believed safe because undefs frequently get turned into 0 either from the constant pool or a desire to not have a false register dependency. But undef is treated specially in some optimizations. For example, its ignored in detection of vector splats. So if the ISD::SHL/SRL can be constant folded and all of the elements with in bounds shift amounts are the same, we might fold it to single element broadcast from the constant pool. This would not put 0s in the elements with out of bounds shift amounts.


Repository:
  rL LLVM

https://reviews.llvm.org/D56695

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrSSE.td
  lib/Target/X86/X86IntrinsicsInfo.h
  test/CodeGen/X86/avx2-intrinsics-x86.ll
  test/CodeGen/X86/avx512-intrinsics.ll
  test/CodeGen/X86/avx512bw-intrinsics.ll
  test/CodeGen/X86/avx512bwvl-intrinsics.ll

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