[PATCH] D56616: [AArch64] Explicitly use v1i64 type for llvm.aarch64.neon.abs.i64 .

[Eli Friedman via Phabricator via llvm-commits]

efriedma marked an inline comment as done.
efriedma added inline comments.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:2726
+      return DAG.getNode(ISD::BITCAST, dl, MVT::i64, Result);
+    } else if (Ty.isVector() && Ty.isInteger() && isTypeLegal(Ty)) {
+      return DAG.getNode(ISD::ABS, dl, Ty, Op.getOperand(1));
----------------
SjoerdMeijer wrote:
> And this is covered by arm64-vabs.ll too. I.e. the tests with llvm.aarch64.neon.abs.v4i32 etc.
> 
> In that case my only nitpick is that we don't need all the curly brackets here but it LGTM to me otherwise.
Normally I don't like mixing brace styles in a single-if-else (it makes it more confusing to figure out where the chain ends).  Not sure how else I would refactor to reduce the number of braces.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56616/new/

https://reviews.llvm.org/D56616