[PATCH] D56281: [DAGCombiner] reduce buildvec of zexted extracted element to shuffle

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:16136
+  SDValue Zext = BV->getOperand(ZextElt);
+  if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() ||
+      Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
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spatel wrote:
> RKSimon wrote:
> > Should ANY_EXTEND be handled as well? SimplifyDemandedBits can reduce ZERO_EXTEND -> ANY_EXTEND more aggressively these days.
> That seems ok, and I can update with a draft of that change. But any idea how to make a test that would provide coverage for that pattern? I'm not showing any existing test diffs. Alternatively, I can add a TODO enhancement comment while trying to find a way to make that happen.
TODO is fine


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56281/new/

https://reviews.llvm.org/D56281