[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

In D53235#1356067 <https://reviews.llvm.org/D53235#1356067>, @rogfer01 wrote:

> Ah, I think what happens is that we should not emit such patterns without the presence of the `F` extension: these patterns are ultimately selected as instructions in `F`. Does this make sense?


Thanks, the code in PerformDAGCombine is incorrectly assuming it will only see f32 if the F extension is enabled. But of course, that's only the case if you're in a post-legalisation combine call. I'll fix and add a test case.


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