[PATCH] D56617: [X86] Avoid clobbering ESP/RSP in the epilogue.

[Geoffry Song via Phabricator via llvm-commits]

goffrie created this revision.
goffrie added a reviewer: rnk.
Herald added a subscriber: llvm-commits.

In r345197 ESP and RSP were added to GR32_TC/GR64_TC, allowing them to
be used for tail calls, but this also caused `findDeadCallerSavedReg` to
think they were acceptable targets for clobbering. Filter them out.

Fixes PR40289.


Repository:
  rL LLVM

https://reviews.llvm.org/D56617

Files:
  lib/Target/X86/X86FrameLowering.cpp
  test/CodeGen/X86/pr40289-64bit.ll
  test/CodeGen/X86/pr40289.ll


Index: test/CodeGen/X86/pr40289.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/pr40289.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s
+
+define < 3 x i32 > @clobber() {
+  %1 = alloca i32
+  %2 = load volatile i32, i32* %1
+  ; CHECK-NOT: popl %esp
+  ; CHECK: addl $4, %esp
+  ret < 3 x i32 > undef
+}
Index: test/CodeGen/X86/pr40289-64bit.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/pr40289-64bit.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s
+
+define cc 92 < 9 x i64 > @clobber() {
+  %1 = alloca i64
+  %2 = load volatile i64, i64* %1
+  ; CHECK-NOT: popq %rsp
+  ; CHECK: addq $8, %rsp
+  ret < 9 x i64 > undef
+}
Index: lib/Target/X86/X86FrameLowering.cpp
===================================================================
--- lib/Target/X86/X86FrameLowering.cpp
+++ lib/Target/X86/X86FrameLowering.cpp
@@ -185,7 +185,8 @@
     }
 
     for (auto CS : AvailableRegs)
-      if (!Uses.count(CS) && CS != X86::RIP)
+      if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
+          CS != X86::ESP)
         return CS;
   }
   }


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