[PATCH] D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 181267.
asb added a comment.

Many thanks to @efriedma for catching the issue with one of the sdiv patterns. I've removed that pattern, and added similar logic to that used for udiv/urem so that anyext is converted to sext if this is likely to result in one of the *w instructions being selected (and thus avoiding unnecessary sext/zext of the input operands).

I've added a comment indicating that srem is believed to be safe (I'd appreciate more eyes, but I believe it's not possible for sexti32 operands to produce a result where res[63:32]=0 and res[31]=1.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53230/new/

https://reviews.llvm.org/D53230

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfoM.td
  test/CodeGen/RISCV/div.ll
  test/CodeGen/RISCV/mul.ll
  test/CodeGen/RISCV/rem.ll
  test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

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