[PATCH] D56596: Enable fma formation for fp16 on x86 and aarch64

[Steve Canon via Phabricator via llvm-commits]

scanon created this revision.
scanon added a reviewer: t.p.northover.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar.

The value of isFMAFasterThanFMulAndFAdd for fp16 should match fp32 on these targets when we legalize by extending to fp32 operations, and (on aarch64) when fp16 arithmetic is supported directly the value should just be true.


Repository:
  rL LLVM

https://reviews.llvm.org/D56596

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/AArch64/f16-instructions.ll


Index: test/CodeGen/AArch64/f16-instructions.ll
===================================================================
--- test/CodeGen/AArch64/f16-instructions.ll
+++ test/CodeGen/AArch64/f16-instructions.ll
@@ -1160,19 +1160,15 @@
 }
 
 ; CHECK-CVT-LABEL: test_fmuladd:
+; CHECK-CVT-NEXT: fcvt s2, h2
 ; CHECK-CVT-NEXT: fcvt s1, h1
 ; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fmul s0, s0, s1
-; CHECK-CVT-NEXT: fcvt h0, s0
-; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fcvt s1, h2
-; CHECK-CVT-NEXT: fadd s0, s0, s1
+; CHECK-CVT-NEXT: fmadd s0, s0, s1, s2
 ; CHECK-CVT-NEXT: fcvt h0, s0
 ; CHECK-CVT-NEXT: ret
 
 ; CHECK-FP16-LABEL: test_fmuladd:
-; CHECK-FP16-NEXT: fmul h0, h0, h1
-; CHECK-FP16-NEXT: fadd h0, h0, h2
+; CHECK-FP16-NEXT: fmadd h0, h0, h1, h2
 ; CHECK-FP16-NEXT: ret
 
 define half @test_fmuladd(half %a, half %b, half %c) #0 {
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -27559,6 +27559,7 @@
     return false;
 
   switch (VT.getSimpleVT().SimpleTy) {
+  case MVT::f16:
   case MVT::f32:
   case MVT::f64:
     return true;
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8678,6 +8678,7 @@
     return false;
 
   switch (VT.getSimpleVT().SimpleTy) {
+  case MVT::f16:
   case MVT::f32:
   case MVT::f64:
     return true;


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