[llvm] r350902 - [MSP430] Add missing instruction forms
Anton Korobeynikov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 10 14:54:54 PST 2019
Author: asl
Date: Thu Jan 10 14:54:53 2019
New Revision: 350902
URL: http://llvm.org/viewvc/llvm-project?rev=350902&view=rev
Log:
[MSP430] Add missing instruction forms
* Add missing mm, [r|m]n, [r|m]p instruction forms.
* Fix bit16mc instruction.
Patch by Kristina Bessonova!
Differential Revision: https://reviews.llvm.org/D56546
Added:
llvm/trunk/test/CodeGen/MSP430/InstII.ll
Modified:
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll
llvm/trunk/test/MC/Disassembler/MSP430/msp430.txt
llvm/trunk/test/MC/MSP430/addrmode.s
llvm/trunk/test/MC/MSP430/const.s
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=350902&r1=350901&r2=350902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Thu Jan 10 14:54:53 2019
@@ -226,7 +226,6 @@ let isCodeGenOnly = 1, usesCustomInserte
// Control Flow Instructions...
//
-// FIXME: Provide proper encoding!
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
def RET : IForm16<0b0100, DstReg, SrcPostInc, 2,
(outs), (ins), "ret", [(MSP430retflag)]> {
@@ -292,6 +291,8 @@ let isCall = 1,
def CALLm : II16m<0b101,
(outs), (ins memsrc:$src),
"call\t$src", [(MSP430call (load addr:$src))]>;
+ def CALLn : II16n<0b101, (outs), (ins indreg:$rs), "call\t$rs", []>;
+ def CALLp : II16p<0b101, (outs), (ins postreg:$rs), "call\t$rs", []>;
}
//===----------------------------------------------------------------------===//
@@ -315,7 +316,6 @@ def PUSH16i : II16i<0b100, (outs), (ins
//===----------------------------------------------------------------------===//
// Move Instructions
-// FIXME: Provide proper encoding!
let hasSideEffects = 0 in {
def MOV8rr : I8rr<0b0100,
(outs GR8:$rd), (ins GR8:$rs),
@@ -327,7 +327,6 @@ def MOV16rr : I16rr<0b0100,
[]>;
}
-// FIXME: Provide proper encoding!
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def MOV8rc : I8rc<0b0100,
(outs GR8:$rd), (ins cg8imm:$imm),
@@ -437,6 +436,11 @@ def MOV16mm : I16mm<0b0100,
"mov\t{$src, $dst}",
[(store (i16 (load addr:$src)), addr:$dst)]>;
+def MOV8mn : I8mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs),
+ "mov.b\t{$rs, $dst}", []>;
+def MOV16mn : I16mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs),
+ "mov\t{$rs, $dst}", []>;
+
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
@@ -619,11 +623,11 @@ def SETZ : InstAlias<"setz", (BIS16rc SR
def : Pat<(MSP430rla GR8:$dst), (ADD8rr $dst, $dst)>;
def : Pat<(MSP430rla GR16:$dst), (ADD16rr $dst, $dst)>;
+// Format-II (Single Operand) Instruction
+// Register mode
let Constraints = "$rs = $rd" in {
let Defs = [SR] in {
-
-// FIXME: memory variant!
def RRA8r : II8r<0b010,
(outs GR8:$rd), (ins GR8:$rs),
"rra.b\t$rd",
@@ -646,9 +650,8 @@ def RRC16r : II16r<0b000,
"rrc\t$rd",
[(set GR16:$rd, (MSP430rrc GR16:$rs)),
(implicit SR)]>;
-}
+} // Uses = [SR]
-// FIXME: Memory sext's ?
def SEXT16r : II16r<0b011,
(outs GR16:$rd), (ins GR16:$rs),
"sxt\t$rd",
@@ -663,7 +666,6 @@ def ZEXT16r : I8rr<0b0100,
"mov.b\t{$rs, $rd}",
[(set GR16:$rd, (zext (trunc GR16:$rs)))]>;
-// FIXME: Memory bitswaps?
def SWPB16r : II16r<0b001,
(outs GR16:$rd), (ins GR16:$rs),
"swpb\t$rd",
@@ -671,6 +673,61 @@ def SWPB16r : II16r<0b001,
} // Constraints = "$src = $dst"
+// Indexed, indirect register and indirect autoincrement modes
+let Defs = [SR] in {
+def RRA8m : II8m<0b010,
+ (outs), (ins memsrc:$src),
+ "rra.b\t$src",
+ [(store (MSP430rra (i8 (load addr:$src))), addr:$src),
+ (implicit SR)]>;
+def RRA16m : II16m<0b010,
+ (outs), (ins memsrc:$src),
+ "rra\t$src",
+ [(store (MSP430rra (i16 (load addr:$src))), addr:$src),
+ (implicit SR)]>;
+
+def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>;
+def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>;
+def RRA8p : II8p<0b010, (outs), (ins postreg:$rs), "rra.b\t$rs", []>;
+def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>;
+
+let Uses = [SR] in {
+def RRC8m : II8m<0b000,
+ (outs), (ins memsrc:$src),
+ "rrc.b\t$src",
+ [(store (MSP430rrc (i8 (load addr:$src))), addr:$src),
+ (implicit SR)]>;
+def RRC16m : II16m<0b000,
+ (outs), (ins memsrc:$src),
+ "rrc\t$src",
+ [(store (MSP430rrc (i16 (load addr:$src))), addr:$src),
+ (implicit SR)]>;
+
+def RRC8n : II8n<0b000, (outs), (ins indreg:$rs), "rrc.b\t$rs", []>;
+def RRC16n : II16n<0b000, (outs), (ins indreg:$rs), "rrc\t$rs", []>;
+def RRC8p : II8p<0b000, (outs), (ins postreg:$rs), "rrc.b\t$rs", []>;
+def RRC16p : II16p<0b000, (outs), (ins postreg:$rs), "rrc\t$rs", []>;
+
+} // Uses = [SR]
+
+def SEXT16m : II16m<0b011,
+ (outs), (ins memsrc:$src),
+ "sxt\t$src",
+ [(store (sext_inreg (extloadi16i8 addr:$src), i8),
+ addr:$src),
+ (implicit SR)]>;
+def SEXT16n : II16n<0b011, (outs), (ins indreg:$rs), "sxt\t$rs", []>;
+def SEXT16p : II16p<0b011, (outs), (ins postreg:$rs), "sxt\t$rs", []>;
+
+} // Defs = [SR]
+
+def SWPB16m : II16m<0b001,
+ (outs), (ins memsrc:$src),
+ "swpb\t$src",
+ [(store (bswap (i16 (load addr:$src))), addr:$src)]>;
+def SWPB16n : II16n<0b001, (outs), (ins indreg:$rs), "swpb\t$rs", []>;
+def SWPB16p : II16p<0b001, (outs), (ins postreg:$rs), "swpb\t$rs", []>;
+
// Integer comparisons
let Defs = [SR] in {
def CMP8rr : I8rr<0b1001,
@@ -733,6 +790,16 @@ def CMP16rm : I16rm<0b1001,
[(MSP430cmp GR16:$rd, (load addr:$src)),
(implicit SR)]>;
+def CMP8rn : I8rn<0b1001,
+ (outs), (ins GR8:$rd, indreg:$rs), "cmp.b\t$rs, $rd", []>;
+def CMP16rn : I16rn<0b1001,
+ (outs), (ins GR16:$rd, indreg:$rs), "cmp\t$rs, $rd", []>;
+
+def CMP8rp : I8rp<0b1001,
+ (outs), (ins GR8:$rd, postreg:$rs), "cmp.b\t$rs, $rd", []>;
+def CMP16rp : I16rp<0b1001,
+ (outs), (ins GR16:$rd, postreg:$rs), "cmp\t$rs, $rd", []>;
+
def CMP8mr : I8mr<0b1001,
(outs), (ins memsrc:$dst, GR8:$rs),
"cmp.b\t$rs, $dst",
@@ -743,6 +810,25 @@ def CMP16mr : I16mr<0b1001,
"cmp\t$rs, $dst",
[(MSP430cmp (load addr:$dst), GR16:$rs),
(implicit SR)]>;
+def CMP8mm : I8mm<0b1001,
+ (outs), (ins memdst:$dst, memsrc:$src),
+ "cmp.b\t$src, $dst",
+ [(MSP430cmp (load addr:$dst), (i8 (load addr:$src))),
+ (implicit SR)]>;
+def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src),
+ "cmp\t$src, $dst",
+ [(MSP430cmp (load addr:$dst), (i16 (load addr:$src))),
+ (implicit SR)]>;
+
+def CMP8mn : I8mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs),
+ "cmp.b\t$rs, $dst", []>;
+def CMP16mn : I16mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs),
+ "cmp\t$rs, $dst", []>;
+
+def CMP8mp : I8mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs),
+ "cmp.b\t$rs, $dst", []>;
+def CMP16mp : I16mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs),
+ "cmp\t$rs, $dst", []>;
// BIT TESTS, just sets condition codes
// Note that the C condition is set differently than when using CMP.
@@ -791,6 +877,16 @@ def BIT16rm : I16rm<0b1011,
[(MSP430cmp (and_su GR16:$rd, (load addr:$src)), 0),
(implicit SR)]>;
+def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs),
+ "bit.b\t$rs, $rd", []>;
+def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs),
+ "bit\t$rs, $rd", []>;
+
+def BIT8rp : I8rp<0b1011, (outs), (ins GR8:$rd, postreg:$rs),
+ "bit.b\t$rs, $rd", []>;
+def BIT16rp : I16rp<0b1011, (outs), (ins GR16:$rd, postreg:$rs),
+ "bit\t$rs, $rd", []>;
+
def BIT8mr : I8mr<0b1011,
(outs), (ins memsrc:$dst, GR8:$rs),
"bit.b\t$rs, $dst",
@@ -808,7 +904,7 @@ def BIT8mc : I8mc<0b1011,
[(MSP430cmp (and_su (load addr:$dst), (i8 cg8imm:$imm)), 0),
(implicit SR)]>;
def BIT16mc : I16mc<0b1011,
- (outs), (ins memsrc:$dst, i16imm:$imm),
+ (outs), (ins memdst:$dst, cg16imm:$imm),
"bit\t$imm, $dst",
[(MSP430cmp (and_su (load addr:$dst), (i16 cg16imm:$imm)), 0),
(implicit SR)]>;
@@ -838,6 +934,16 @@ def BIT16mm : I16mm<0b1011,
(load addr:$src)),
0),
(implicit SR)]>;
+def BIT8mn : I8mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs),
+ "bit.b\t$rs, $dst", []>;
+def BIT16mn : I16mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs),
+ "bit\t$rs, $dst", []>;
+
+def BIT8mp : I8mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs),
+ "bit.b\t$rs, $dst", []>;
+def BIT16mp : I16mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs),
+ "bit\t$rs, $dst", []>;
+
} // Defs = [SR]
def TST8r : InstAlias<"tst.b\t$dst", (CMP8rc GR8:$dst, 0)>;
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll?rev=350902&r1=350901&r2=350902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll Thu Jan 10 14:54:53 2019
@@ -67,3 +67,22 @@ entry:
; CHECK-DAG: mov 2(r1), 6(r1)
; CHECK-DAG: mov 0(r1), 4(r1)
}
+
+define void @cmp(i16* %g, i16* %i) {
+entry:
+; CHECK-LABEL: cmp:
+; CHECK: cmp 8(r12), 4(r13)
+ %add.ptr = getelementptr inbounds i16, i16* %g, i16 4
+ %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr1 = getelementptr inbounds i16, i16* %i, i16 2
+ %1 = load i16, i16* %add.ptr1, align 2
+ %cmp = icmp sgt i16 %0, %1
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i16 0, i16* %g, align 2
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll?rev=350902&r1=350901&r2=350902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll Thu Jan 10 14:54:53 2019
@@ -53,3 +53,21 @@ define void @xor() nounwind {
ret void
}
+define void @cmp(i8* %g, i8* %i) {
+entry:
+; CHECK-LABEL: cmp:
+; CHECK: cmp.b 4(r12), 2(r13)
+ %add.ptr = getelementptr inbounds i8, i8* %g, i16 4
+ %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr1 = getelementptr inbounds i8, i8* %i, i16 2
+ %1 = load i8, i8* %add.ptr1, align 1
+ %cmp = icmp sgt i8 %0, %1
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i8 0, i8* %g, align 2
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
Added: llvm/trunk/test/CodeGen/MSP430/InstII.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/InstII.ll?rev=350902&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/InstII.ll (added)
+++ llvm/trunk/test/CodeGen/MSP430/InstII.ll Thu Jan 10 14:54:53 2019
@@ -0,0 +1,68 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define void @rra8m(i8* %i) {
+entry:
+; CHECK-LABEL: rra8m:
+; CHECK: rra.b 2(r12)
+ %0 = getelementptr inbounds i8, i8* %i, i16 2
+ %1 = load i8, i8* %0, align 1
+ %shr = ashr i8 %1, 1
+ store i8 %shr, i8* %0, align 1
+ ret void
+}
+
+define void @rra16m(i16* %i) {
+entry:
+; CHECK-LABEL: rra16m:
+; CHECK: rra 4(r12)
+ %0 = getelementptr inbounds i16, i16* %i, i16 2
+ %1 = load i16, i16* %0, align 2
+ %shr = ashr i16 %1, 1
+ store i16 %shr, i16* %0, align 2
+ ret void
+}
+
+; TODO: `clrc; rrc.b 2(r12)` is expected
+define void @rrc8m(i8* %g) {
+entry:
+; CHECK-LABEL: rrc8m:
+; CHECK: mov.b 2(r12), r13
+; CHECK: clrc
+; CHECK: rrc.b r13
+; CHECK: mov.b r13, 2(r12)
+ %add.ptr = getelementptr inbounds i8, i8* %g, i16 2
+ %0 = load i8, i8* %add.ptr, align 1
+ %1 = lshr i8 %0, 1
+ store i8 %1, i8* %add.ptr, align 1
+ ret void
+}
+
+; TODO: `clrc; rrc 4(r12)` is expected
+define void @rrc16m(i16* %g) {
+entry:
+; CHECK-LABEL: rrc16m:
+; CHECK: mov 4(r12), r13
+; CHECK: clrc
+; CHECK: rrc r13
+; CHECK: mov r13, 4(r12)
+ %add.ptr = getelementptr inbounds i16, i16* %g, i16 2
+ %0 = load i16, i16* %add.ptr, align 2
+ %shr = lshr i16 %0, 1
+ store i16 %shr, i16* %add.ptr, align 2
+ ret void
+}
+
+define void @sxt16m(i16* %x) {
+entry:
+; CHECK-LABEL: sxt16m:
+; CHECK: sxt 4(r12)
+ %add.ptr = getelementptr inbounds i16, i16* %x, i16 2
+ %0 = bitcast i16* %add.ptr to i8*
+ %1 = load i8, i8* %0, align 1
+ %conv = sext i8 %1 to i16
+ store i16 %conv, i16* %add.ptr, align 2
+ ret void
+}
+
Modified: llvm/trunk/test/MC/Disassembler/MSP430/msp430.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/MSP430/msp430.txt?rev=350902&r1=350901&r2=350902&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/MSP430/msp430.txt (original)
+++ llvm/trunk/test/MC/Disassembler/MSP430/msp430.txt Thu Jan 10 14:54:53 2019
@@ -19,9 +19,10 @@
0x1f 0x40 0x2a 0x00 # CHECK: mov 42, r15
0xb0 0x12 0x81 0x01 # CHECK: call #385
0x97 0x12 0x06 0x00 # CHECK: call 6(r7)
-0xa7 0xb2 0x02 0x00 # CHECK: bit #34, 2(r7)
+0xa7 0xb2 0x02 0x00 # CHECK: bit #4, 2(r7)
0xa9 0x57 0x08 0x00 # CHECK: add @r7, 8(r9)
0xb7 0xe7 0xfe 0xff # CHECK: xor @r7+, -2(r7)
0xbf 0x40 0x2a 0x00 0x0c 0x00 # CHECK: mov #42, 12(r15)
+0xb7 0xb0 0x22 0x00 0x02 0x00 # CHECK: bit #34, 2(r7)
0x9a 0xb9 0x10 0x00 0x08 0x00 # CHECK: bit 16(r9), 8(r10)
Modified: llvm/trunk/test/MC/MSP430/addrmode.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MSP430/addrmode.s?rev=350902&r1=350901&r2=350902&view=diff
==============================================================================
--- llvm/trunk/test/MC/MSP430/addrmode.s (original)
+++ llvm/trunk/test/MC/MSP430/addrmode.s Thu Jan 10 14:54:53 2019
@@ -93,6 +93,8 @@ foo:
call r7
call 6(r7)
+ call @r7
+ call @r7+
call disp+6(r7)
call &disp
call disp
@@ -100,11 +102,61 @@ foo:
; CHECK: call r7 ; encoding: [0x87,0x12]
; CHECK: call 6(r7) ; encoding: [0x97,0x12,0x06,0x00]
+; CHECK: call @r7 ; encoding: [0xa7,0x12]
+; CHECK: call @r7+ ; encoding: [0xb7,0x12]
; CHECK: call disp+6(r7) ; encoding: [0x97,0x12,A,A]
; CHECK: call &disp ; encoding: [0x92,0x12,A,A]
; CHECK: call disp ; encoding: [0x90,0x12,A,A]
; CHECK: call #disp ; encoding: [0xb0,0x12,A,A]
+ rra r7 ; CHECK: rra r7 ; encoding: [0x07,0x11]
+ rra 2(r7) ; CHECK: rra 2(r7) ; encoding: [0x17,0x11,0x02,0x00]
+ rra @r7 ; CHECK: rra @r7 ; encoding: [0x27,0x11]
+ rra @r7+ ; CHECK: rra @r7+ ; encoding: [0x37,0x11]
+
+ rrc r7 ; CHECK: rrc r7 ; encoding: [0x07,0x10]
+ rrc 2(r7) ; CHECK: rrc 2(r7) ; encoding: [0x17,0x10,0x02,0x00]
+ rrc @r7 ; CHECK: rrc @r7 ; encoding: [0x27,0x10]
+ rrc @r7+ ; CHECK: rrc @r7+ ; encoding: [0x37,0x10]
+
+ swpb r7 ; CHECK: swpb r7 ; encoding: [0x87,0x10]
+ swpb 2(r7) ; CHECK: swpb 2(r7) ; encoding: [0x97,0x10,0x02,0x00]
+ swpb @r7 ; CHECK: swpb @r7 ; encoding: [0xa7,0x10]
+ swpb @r7+ ; CHECK: swpb @r7+ ; encoding: [0xb7,0x10]
+
+ sxt r7 ; CHECK: sxt r7 ; encoding: [0x87,0x11]
+ sxt 2(r7) ; CHECK: sxt 2(r7) ; encoding: [0x97,0x11,0x02,0x00]
+ sxt @r7 ; CHECK: sxt @r7 ; encoding: [0xa7,0x11]
+ sxt @r7+ ; CHECK: sxt @r7+ ; encoding: [0xb7,0x11]
+
+ cmp r5, r7 ; CHECK: cmp r5, r7 ; encoding: [0x07,0x95]
+ cmp 2(r5), r7 ; CHECK: cmp 2(r5), r7 ; encoding: [0x17,0x95,0x02,0x00]
+ cmp #-1, r7 ; CHECK: cmp #-1, r7 ; encoding: [0x37,0x93]
+ cmp #42, r7 ; CHECK: cmp #42, r7 ; encoding: [0x37,0x90,0x2a,0x00]
+ cmp @r5, r7 ; CHECK: cmp @r5, r7 ; encoding: [0x27,0x95]
+ cmp @r5+, r7 ; CHECK: cmp @r5+, r7 ; encoding: [0x37,0x95]
+
+ cmp r5, 2(r7) ; CHECK: cmp r5, 2(r7) ; encoding: [0x87,0x95,0x02,0x00]
+ cmp 2(r7), 2(r7) ; CHECK: cmp 2(r7), 2(r7) ; encoding: [0x97,0x97,0x02,0x00,0x02,0x00]
+ cmp #-1, 2(r7) ; CHECK: cmp #-1, 2(r7) ; encoding: [0xb7,0x93,0x02,0x00]
+ cmp #42, 2(r7) ; CHECK: cmp #42, 2(r7) ; encoding: [0xb7,0x90,0x2a,0x00,0x02,0x00]
+ cmp @r5, 2(r7) ; CHECK: cmp @r5, 2(r7) ; encoding: [0xa7,0x95,0x02,0x00]
+ cmp @r5+, 2(r7) ; CHECK: cmp @r5+, 2(r7) ; encoding: [0xb7,0x95,0x02,0x00]
+
+ bit r5, r7 ; CHECK: bit r5, r7 ; encoding: [0x07,0xb5]
+ bit 2(r5), r7 ; CHECK: bit 2(r5), r7 ; encoding: [0x17,0xb5,0x02,0x00]
+ bit #-1, r7 ; CHECK: bit #-1, r7 ; encoding: [0x37,0xb3]
+ bit #42, r7 ; CHECK: bit #42, r7 ; encoding: [0x37,0xb0,0x2a,0x00]
+ bit @r5, r7 ; CHECK: bit @r5, r7 ; encoding: [0x27,0xb5]
+ bit @r5+, r7 ; CHECK: bit @r5+, r7 ; encoding: [0x37,0xb5]
+
+ bit r5, 2(r7) ; CHECK: bit r5, 2(r7) ; encoding: [0x87,0xb5,0x02,0x00]
+ bit 2(r7), 2(r7) ; CHECK: bit 2(r7), 2(r7) ; encoding: [0x97,0xb7,0x02,0x00,0x02,0x00]
+ bit #-1, 2(r7) ; CHECK: bit #-1, 2(r7) ; encoding: [0xb7,0xb3,0x02,0x00]
+ bit #42, 2(r7) ; CHECK: bit #42, 2(r7) ; encoding: [0xb7,0xb0,0x2a,0x00,0x02,0x00]
+ bit @r5, 2(r7) ; CHECK: bit @r5, 2(r7) ; encoding: [0xa7,0xb5,0x02,0x00]
+ bit @r5+, 2(r7) ; CHECK: bit @r5+, 2(r7) ; encoding: [0xb7,0xb5,0x02,0x00]
+
disp:
.word 0xcafe
.word 0xbabe
Modified: llvm/trunk/test/MC/MSP430/const.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MSP430/const.s?rev=350902&r1=350901&r2=350902&view=diff
==============================================================================
--- llvm/trunk/test/MC/MSP430/const.s (original)
+++ llvm/trunk/test/MC/MSP430/const.s Thu Jan 10 14:54:53 2019
@@ -1,10 +1,13 @@
; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s
- mov #4, r15 ; CHECK: mov #4, r15 ; encoding: [0x2f,0x42]
- mov #8, r15 ; CHECK: mov #8, r15 ; encoding: [0x3f,0x42]
- mov #0, r15 ; CHECK: clr r15 ; encoding: [0x0f,0x43]
- mov #1, r15 ; CHECK: mov #1, r15 ; encoding: [0x1f,0x43]
- mov #2, r15 ; CHECK: mov #2, r15 ; encoding: [0x2f,0x43]
- mov #-1, r7 ; CHECK: mov #-1, r7 ; encoding: [0x37,0x43]
- push #8 ; CHECK: push #8 ; encoding: [0x32,0x12]
- push #42 ; CHECK: push #42 ; encoding: [0x30,0x12,0x2a,0x00]
+ mov #4, r15 ; CHECK: mov #4, r15 ; encoding: [0x2f,0x42]
+ mov #8, r15 ; CHECK: mov #8, r15 ; encoding: [0x3f,0x42]
+ mov #0, r15 ; CHECK: clr r15 ; encoding: [0x0f,0x43]
+ mov #1, r15 ; CHECK: mov #1, r15 ; encoding: [0x1f,0x43]
+ mov #2, r15 ; CHECK: mov #2, r15 ; encoding: [0x2f,0x43]
+ mov #-1, r7 ; CHECK: mov #-1, r7 ; encoding: [0x37,0x43]
+
+ push #8 ; CHECK: push #8 ; encoding: [0x32,0x12]
+ push #42 ; CHECK: push #42 ; encoding: [0x30,0x12,0x2a,0x00]
+
+ bit #1, 0(r7) ; CHECK: bit #1, 0(r7) ; encoding: [0x97,0xb3,0x00,0x00]
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