[PATCH] D55639: GlobalISel: Allow shift amount to be a different type
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 10 04:07:27 PST 2019
arsenm marked 3 inline comments as done.
arsenm added inline comments.
================
Comment at: lib/Target/X86/X86InstructionSelector.cpp:1546
return false;
auto ShiftEntryIt = std::find_if(
----------------
igorb wrote:
> please add assert, insure Operand(2) size is 8bit
I think this is redundant since the verifier will catch the mismatched sizes with COPY to CL
================
Comment at: lib/Target/X86/X86RegisterBankInfo.cpp:189
+
+ const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
----------------
igorb wrote:
> This code is similar to getSameOperandsMapping(..) .
> Could you please modify getSameOperandsMapping to handle this case?
I wasn't sure what the "Same" was referring to here. Since it specifically asserts for mismatched types, I figured this for some reason cared about operands all with the same size. It probably needs a new name, but I'm not sure what it should be here without knowing more about x86's register banks.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D55639/new/
https://reviews.llvm.org/D55639
More information about the llvm-commits
mailing list