[llvm] r350588 - AMDGPU/GlobalISel: InstrMapping for G_UNMERGE_VALUES

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Jan  7 16:46:19 2019
New Revision: 350588

URL: http://llvm.org/viewvc/llvm-project?rev=350588&view=rev
Log:
AMDGPU/GlobalISel: InstrMapping for G_UNMERGE_VALUES

Added:
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=350588&r1=350587&r2=350588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Mon Jan  7 16:46:19 2019
@@ -562,6 +562,18 @@ AMDGPURegisterBankInfo::getInstrMapping(
 
     break;
   }
+  case AMDGPU::G_UNMERGE_VALUES: {
+    unsigned Bank = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
+      AMDGPU::VGPRRegBankID;
+
+    // Op1 and Dst should use the same register bank.
+    // FIXME: Shouldn't this be the default? Why do we need to handle this?
+    for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+      unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
+      OpdsMapping[i] = AMDGPU::getValueMapping(Bank, Size);
+    }
+    break;
+  }
   case AMDGPU::G_INTRINSIC: {
     switch (MI.getOperand(1).getIntrinsicID()) {
     default:

Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir?rev=350588&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir Mon Jan  7 16:46:19 2019
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+
+---
+name: test_unmerge_s64_s32_s
+legalized: true
+
+body: |
+  bb.0:
+   liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: test_unmerge_s64_s32_s
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+    ; CHECK: $vgpr0 = COPY [[UV]](s32)
+    ; CHECK: $vgpr2 = COPY [[UV]](s32)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64)
+    $vgpr0 = COPY %1(s32)
+    $vgpr2 = COPY %1(s32)
+...
+
+---
+name: test_unmerge_s64_s32_v
+legalized: true
+
+body: |
+  bb.0:
+   liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: test_unmerge_s64_s32_v
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+    ; CHECK: $vgpr0 = COPY [[UV]](s32)
+    ; CHECK: $vgpr2 = COPY [[UV]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64)
+    $vgpr0 = COPY %1(s32)
+    $vgpr2 = COPY %1(s32)
+...