[PATCH] D56264: [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:543
+    if (N->getValueType(0) != MVT::i32 || RHS->getOpcode() == ISD::Constant ||
+        (RHS->getOpcode() == ISD::AssertZext))
+      break;
----------------
Is it worth detecting an existing AssertZext with a value type wider than 5 bits?


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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:667
+def assertzexti5 : PatFrag<(ops node:$src), (assertzext node:$src), [{
+  return cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits() == 5;
+}]>;
----------------
`<= 5`?


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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:673
+def shiftwamt : PatFrags<(ops node:$src),
+                         [(assertzexti5 (and node:$src, 0xffffffff)),
+                          (assertzexti5 node:$src)]>;
----------------
The literal "0xffffffff" could probably be generalized a bit.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56264/new/

https://reviews.llvm.org/D56264