[llvm] r350514 - Regenerate test.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Jan  7 04:21:13 2019
New Revision: 350514

URL: http://llvm.org/viewvc/llvm-project?rev=350514&view=rev
Log:
Regenerate test.

Prep work towards enabling SimplifyDemandedBits vector support for TRUNCATE as discussed on D56118.

Modified:
    llvm/trunk/test/CodeGen/ARM/lowerMUL-newload.ll

Modified: llvm/trunk/test/CodeGen/ARM/lowerMUL-newload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lowerMUL-newload.ll?rev=350514&r1=350513&r2=350514&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/lowerMUL-newload.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/lowerMUL-newload.ll Mon Jan  7 04:21:13 2019
@@ -1,25 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=krait | FileCheck %s
 
 define void @func1(i16* %a, i16* %b, i16* %c) {
+; CHECK-LABEL: func1:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    add r3, r1, #16
+; CHECK-NEXT:    vldr d18, [r2, #16]
+; CHECK-NEXT:    vld1.16 {d16}, [r3:64]
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    vaddw.s16 q10, q8, d18
+; CHECK-NEXT:    vmovn.i32 d19, q10
+; CHECK-NEXT:    vldr d20, [r0, #16]
+; CHECK-NEXT:    vstr d19, [r0, #16]
+; CHECK-NEXT:    vldr d19, [r2, #16]
+; CHECK-NEXT:    vmull.s16 q11, d18, d19
+; CHECK-NEXT:    vmovl.s16 q9, d19
+; CHECK-NEXT:    vmla.i32 q11, q8, q9
+; CHECK-NEXT:    vmovn.i32 d16, q11
+; CHECK-NEXT:    vstr d16, [r1, #16]
+; CHECK-NEXT:    vldr d16, [r2, #16]
+; CHECK-NEXT:    vmlal.s16 q11, d16, d20
+; CHECK-NEXT:    vmovn.i32 d16, q11
+; CHECK-NEXT:    vstr d16, [r0, #16]
+; CHECK-NEXT:    bx lr
 entry:
 ; The test case trying to vectorize the pseudo code below.
 ; a[i] = b[i] + c[i];
 ; b[i] = a[i] * c[i];
 ; a[i] = b[i] + a[i] * c[i];
-;
 ; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i]" is
 ; scheduled before the first vector store to "a[i] = b[i] + c[i]".
 ; Checking that there is no vector load a[i] scheduled between the vector
 ; stores to a[i], otherwise the load of a[i] will be polluted by the first
 ; vector store to a[i].
-;
 ; This test case check that the chain information is updated during
 ; lowerMUL for the new created Load SDNode.
 
-; CHECK: vldr {{.*}} [r0, #16]
-; CHECK: vstr {{.*}} [r0, #16]
-; CHECK-NOT: vldr {{.*}} [r0, #16]
-; CHECK: vstr {{.*}} [r0, #16]
 
   %scevgep0 = getelementptr i16, i16* %a, i32 8
   %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
@@ -57,26 +73,41 @@ entry:
 }
 
 define void @func2(i16* %a, i16* %b, i16* %c) {
+; CHECK-LABEL: func2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    add r3, r1, #16
+; CHECK-NEXT:    vldr d18, [r2, #16]
+; CHECK-NEXT:    vld1.16 {d16}, [r3:64]
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    vaddw.s16 q10, q8, d18
+; CHECK-NEXT:    vmovn.i32 d19, q10
+; CHECK-NEXT:    vldr d20, [r0, #16]
+; CHECK-NEXT:    vstr d19, [r0, #16]
+; CHECK-NEXT:    vldr d19, [r2, #16]
+; CHECK-NEXT:    vmull.s16 q11, d18, d19
+; CHECK-NEXT:    vmovl.s16 q9, d19
+; CHECK-NEXT:    vmla.i32 q11, q8, q9
+; CHECK-NEXT:    vmovn.i32 d16, q11
+; CHECK-NEXT:    vstr d16, [r1, #16]
+; CHECK-NEXT:    vldr d16, [r2, #16]
+; CHECK-NEXT:    vmlal.s16 q11, d16, d20
+; CHECK-NEXT:    vaddw.s16 q8, q11, d20
+; CHECK-NEXT:    vmovn.i32 d16, q8
+; CHECK-NEXT:    vstr d16, [r0, #16]
+; CHECK-NEXT:    bx lr
 entry:
 ; The test case trying to vectorize the pseudo code below.
 ; a[i] = b[i] + c[i];
 ; b[i] = a[i] * c[i];
 ; a[i] = b[i] + a[i] * c[i] + a[i];
-;
 ; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i] + a[i]"
 ; is scheduled before the first vector store to "a[i] = b[i] + c[i]".
 ; Checking that there is no vector load a[i] scheduled between the first
 ; vector store to a[i] and the vector add of a[i], otherwise the load of
 ; a[i] will be polluted by the first vector store to a[i].
-;
 ; This test case check that both the chain and value of the new created
 ; Load SDNode are updated during lowerMUL.
 
-; CHECK: vldr {{.*}} [r0, #16]
-; CHECK: vstr {{.*}} [r0, #16]
-; CHECK-NOT: vldr {{.*}} [r0, #16]
-; CHECK: vaddw.s16
-; CHECK: vstr {{.*}} [r0, #16]
 
   %scevgep0 = getelementptr i16, i16* %a, i32 8
   %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*