[PATCH] D56296: [AArch64] Fix operation actions for FP16 vector intrinsics

[Bryan Chan via Phabricator via llvm-commits]

bryanpkc created this revision.
bryanpkc added reviewers: t.p.northover, SjoerdMeijer.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar.

This patch changes the legalization action for some half-precision floating-
point vector intrinsics (FSIN, FLOG, etc.) from Promote to Expand. These ops
are not supported in hardware for half-precision vectors, but promotion is
not always possible (for v8f16 operands). Changing the action to Expand fixes
an assertion failure in the legalizer when the frontend produces such ops.
In addition, a quick microbenchmark shows that, in the v4f16 case,
expanding introduces fewer spills and is therefore slightly faster than
promoting.


Repository:
  rL LLVM

https://reviews.llvm.org/D56296

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-vfloatintrinsics.ll

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