[llvm] r350353 - [AVR] Update integration/blink.ll as we now generate sbi/cbi instructions.

[Nirav Dave via llvm-commits]

Author: niravd
Date: Thu Jan  3 13:25:39 2019
New Revision: 350353

URL: http://llvm.org/viewvc/llvm-project?rev=350353&view=rev
Log:
[AVR] Update integration/blink.ll as we now generate sbi/cbi instructions.

Silence long standing test failure.

Modified:
    llvm/trunk/test/CodeGen/AVR/integration/blink.ll

Modified: llvm/trunk/test/CodeGen/AVR/integration/blink.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/integration/blink.ll?rev=350353&r1=350352&r2=350353&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/integration/blink.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/integration/blink.ll Thu Jan  3 13:25:39 2019
@@ -34,15 +34,8 @@
 define void @setup_ddr() {
 entry:
 
-  ; This should load the value of DDRB, OR it with the bit number and store
-  ; the result back to DDRB.
-
-  ; CHECK:      in      [[TMPREG:r[0-9]+]], 4
-  ; CHECK-NEXT: ori     [[TMPREG]], 32
-
-  ; CHECK-NOT: ori     {{r[0-9]+}}, 0
-
-  ; CHECK-NEXT: out     4, [[TMPREG]]
+  ; This should set the 5th bit of DDRB.
+  ; CHECK:      sbi	4, 5
   ; CHECK-NEXT: ret
 
   %0 = load volatile i8, i8* inttoptr (i16 36 to i8*), align 1
@@ -58,15 +51,8 @@ entry:
 define void @turn_on() {
 entry:
 
-  ; This should load the value of PORTB, OR it with the bit number and store
-  ; the result back to DDRB.
-
-  ; CHECK:      in      [[TMPREG:r[0-9]+]], 5
-  ; CHECK-NEXT: ori     [[TMPREG]], 32
-
-  ; CHECK-NOT: ori     {{r[0-9]+}}, 0
-
-  ; CHECK-NEXT: out     5, [[TMPREG]]
+  ; This should set the 5th bit of PORTB
+  ; CHECK:      sbi	5, 5
   ; CHECK-NEXT: ret
 
   %0 = load volatile i8, i8* inttoptr (i16 37 to i8*), align 1
@@ -82,14 +68,8 @@ entry:
 define void @turn_off() {
 entry:
 
-  ; This should load the value of PORTB, OR it with the bit number and store
-  ; the result back to DDRB.
-
-
-  ; CHECK:      in      [[TMPREG:r[0-9]+]], 5
-  ; CHECK-NEXT: andi    [[TMPREG]], 223
-  ; CHECK-NEXT: andi    {{r[0-9]+}}, 0
-  ; CHECK-NEXT: out     5, [[TMPREG]]
+  ; This should clear the 5th bit of PORTB
+  ; CHECK:      cbi     5, 5
   ; CHECK-NEXT: ret
 
   %0 = load volatile i8, i8* inttoptr (i16 37 to i8*), align 1