[PATCH] D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 180031.
asb edited the summary of this revision.
asb added a reviewer: eli.friedman.
asb added a comment.

Updated the patch to address the correctness issues with the udiv and urem patterns. Like with D56264 <https://reviews.llvm.org/D56264>, a dag combine converts an ANY_EXTEND to a SIGN_EXTEND when it operates on an instruction where a 32-bit *W variant could be selected. This is advantageous as it can avoid unnecessary masking/sign-extension of the input operands.

See also the related discussion on llvm-dev http://lists.llvm.org/pipermail/llvm-dev/2018-December/128497.html


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53230/new/

https://reviews.llvm.org/D53230

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfoM.td
  test/CodeGen/RISCV/div.ll
  test/CodeGen/RISCV/mul.ll
  test/CodeGen/RISCV/rem.ll
  test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

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