[PATCH] D56199: [X86] Support SHLD/SHRD masked shift-counts (PR34641)

[Sanjay Patel via Phabricator via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:36543-36545
+  if (ShAmt0.getOpcode() == ISD::AND)
+    if (auto *ShMsk0Cst = dyn_cast<ConstantSDNode>(ShAmt0.getOperand(1)))
+      if (ShMsk0Cst->getAPIntValue() == (Bits - 1)) {
----------------
Matter of taste, but we could avoid the partial-braces/indenting with something like:
  if (ShAmt0.getOpcode() == ISD::AND &&
      isa<ConstantSDNode>(ShAmt0.getOperand(1)) &&
      ShAmt0.getConstantOperandVal(1) == Bits - 1)



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  https://reviews.llvm.org/D56199/new/

https://reviews.llvm.org/D56199