[PATCH] D56156: [DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, efriedma.
Herald added subscribers: jsji, kbarton, nemanjai.

If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead.

The X86 setcc-combine.ll changes are a little weird, but probably not much of a performance difference. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I can see a couple ways to fix this. Early exit from visitTRUNCATE if its used by a sext similar to what is done for aext. This is tricky because we aren't always able to optimize a sext+trunc. The other option is to change type legalization to promote extractvectorelt inputs and result type simultaneously. If we promote the result first we can temporarily have an extractvectorelt with a result type we never really wanted.


Repository:
  rL LLVM

https://reviews.llvm.org/D56156

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/PowerPC/f128-truncateNconv.ll
  test/CodeGen/PowerPC/ppc64-P9-setb.ll
  test/CodeGen/X86/setcc-combine.ll
  test/CodeGen/X86/vsel-cmp-load.ll

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