[llvm] r350126 - [AArch64] Add command-line option for SB
Diogo N. Sampaio via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 28 09:14:58 PST 2018
Author: dnsampaio
Date: Fri Dec 28 09:14:58 2018
New Revision: 350126
URL: http://llvm.org/viewvc/llvm-project?rev=350126&view=rev
Log:
[AArch64] Add command-line option for SB
SB (Speculative Barrier) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SB, as it was previously only possible to
enable by selecting -march=armv8.5-a.
This patch also moves to FeatureSB the old FeatureSpecRestrict.
Reviewers: pbarrio, olista01, t.p.northover, LukeCheeseman
Differential Revision: https://reviews.llvm.org/D55921
Added:
llvm/trunk/test/MC/AArch64/armv8.5a-sb.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
Removed:
llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt
Modified:
llvm/trunk/include/llvm/Support/AArch64TargetParser.def
llvm/trunk/include/llvm/Support/AArch64TargetParser.h
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/unittests/Support/TargetParserTest.cpp
Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=350126&r1=350125&r2=350126&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Fri Dec 28 09:14:58 2018
@@ -73,6 +73,7 @@ AARCH64_ARCH_EXT_NAME("rcpc", AArch6
AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
+AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.h?rev=350126&r1=350125&r2=350126&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.h (original)
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.h Fri Dec 28 09:14:58 2018
@@ -48,6 +48,7 @@ enum ArchExtKind : unsigned {
AEK_RAND = 1 << 18,
AEK_MTE = 1 << 19,
AEK_SSBS = 1 << 20,
+ AEK_SB = 1 << 21,
};
enum class ArchKind {
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=350126&r1=350125&r2=350126&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Fri Dec 28 09:14:58 2018
@@ -306,12 +306,12 @@ def FeatureFRInt3264 : SubtargetFeature<
def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction" >;
+def FeatureSB : SubtargetFeature<"sb", "HasSB",
+ "true", "Enable v8.5 Speculation Barrier" >;
+
def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
"true", "Enable Speculative Store Bypass Safe bit" >;
-def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
- "Enable speculation control barrier" >;
-
def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
"Enable execution and data prediction invalidation instructions" >;
@@ -352,7 +352,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
- FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
+ FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist,
FeatureBranchTargetId]
>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=350126&r1=350125&r2=350126&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Fri Dec 28 09:14:58 2018
@@ -114,8 +114,8 @@ def HasAltNZCV : Predicate<"Subtar
AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">;
def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
-def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
- AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
+def HasSB : Predicate<"Subtarget->hasSB()">,
+ AssemblerPredicate<"FeatureSB", "sb">;
def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">,
AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
@@ -733,7 +733,7 @@ def AXFLAG : PstateWriteSimple<(ins), "a
def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {
let Inst{20-5} = 0b0001100110000111;
let Unpredictable{11-8} = 0b1111;
- let Predicates = [HasSpecCtrl];
+ let Predicates = [HasSB];
let hasSideEffects = 1;
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=350126&r1=350125&r2=350126&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Fri Dec 28 09:14:58 2018
@@ -126,8 +126,8 @@ protected:
bool HasAlternativeNZCV = false;
bool HasFRInt3264 = false;
bool HasSpecRestrict = false;
- bool HasSpecCtrl = false;
bool HasSSBS = false;
+ bool HasSB = false;
bool HasPredCtrl = false;
bool HasCCDP = false;
bool HasBTI = false;
@@ -355,8 +355,8 @@ public:
bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
bool hasFRInt3264() const { return HasFRInt3264; }
bool hasSpecRestrict() const { return HasSpecRestrict; }
- bool hasSpecCtrl() const { return HasSpecCtrl; }
bool hasSSBS() const { return HasSSBS; }
+ bool hasSB() const { return HasSB; }
bool hasPredCtrl() const { return HasPredCtrl; }
bool hasCCDP() const { return HasCCDP; }
bool hasBTI() const { return HasBTI; }
Added: llvm/trunk/test/MC/AArch64/armv8.5a-sb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-sb.s?rev=350126&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-sb.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-sb.s Fri Dec 28 09:14:58 2018
@@ -0,0 +1,11 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sb -o - %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a -o - %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-sb -o - %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+// Flag manipulation
+sb
+
+// CHECK: sb // encoding: [0xff,0x30,0x03,0xd5]
+
+// NOSB: instruction requires: sb
+// NOSB-NEXT: sb
Removed: llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s?rev=350125&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s (removed)
@@ -1,11 +0,0 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specctrl < %s | FileCheck %s
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-
-// Flag manipulation
-sb
-
-// CHECK: sb // encoding: [0xff,0x30,0x03,0xd5]
-
-// NOSB: instruction requires: specctrl
-// NOSB-NEXT: sb
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-sb.txt?rev=350126&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-sb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-sb.txt Fri Dec 28 09:14:58 2018
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+# New reg
+0xff 0x30 0x03 0xd5
+
+# CHECK: sb
+# NOSB: msr S0_3_C3_C0_7, xzr
Removed: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt?rev=350125&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt (removed)
@@ -1,9 +0,0 @@
-# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+specctrl -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-
-# New reg
-0xff 0x30 0x03 0xd5
-
-# CHECK: sb
-# NOSB: msr S0_3_C3_C0_7, xzr
Modified: llvm/trunk/unittests/Support/TargetParserTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=350126&r1=350125&r2=350126&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/TargetParserTest.cpp (original)
+++ llvm/trunk/unittests/Support/TargetParserTest.cpp Fri Dec 28 09:14:58 2018
@@ -988,7 +988,8 @@ TEST(TargetParserTest, AArch64ArchExtFea
{"rcpc", "norcpc", "+rcpc", "-rcpc" },
{"rng", "norng", "+rand", "-rand"},
{"memtag", "nomemtag", "+mte", "-mte"},
- {"ssbs", "nossbs", "+ssbs", "-ssbs"}};
+ {"ssbs", "nossbs", "+ssbs", "-ssbs"},
+ {"sb", "nosb", "+sb", "-sb"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),
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