[PATCH] D56098: [ARM] Teach ComputeKnownBits to handle extract vectors

[silviu.baranga@arm.com via Phabricator via llvm-commits]

sbaranga added inline comments.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:13639
+    const SDValue &SrcSV = Op.getOperand(0);
+    Known = DAG.computeKnownBits(SrcSV, Depth + 1);
+    EVT VT = Op.getValueType();
----------------
IIUC we're computing here the known bits on the input vector operand. However, when computing the result of the VGETLANE operation we're not taking into account the lane operand, which seems wrong to me.

We should have additional tests to cover both the sext and zext cases and cases where the lane operand is not zero.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:13656
+  }
+  assert(DstSz == Known.getBitWidth());
   }
----------------
Is this assert unreachable?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56098/new/

https://reviews.llvm.org/D56098