[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev marked an inline comment as done.
anton-afanasyev added inline comments.


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Comment at: lib/Target/X86/X86TargetTransformInfo.cpp:150
 
+unsigned X86TTIImpl::getMinVectorRegisterBitWidth() const {
+  return 64;
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RKSimon wrote:
> Can we add a IsFloat bool argument here?
That is not possible: at this stage we can only operate by vector register width notion regardless of the scalars type. And what is the cause we can need it?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082