[PATCH] D56077: [PowerPC] Fix assert from machine verify pass that atomic pseudo expanding causes mismatched register class

[Hal Finkel via Phabricator via llvm-commits]

hfinkel accepted this revision.
hfinkel added a comment.
This revision is now accepted and ready to land.

Please fixup the comments, but LGTM.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9982
   }
-  BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+  // We need use 32-bit subregister to avoid
+  // mismatch register class in 64-bit mode
----------------
This comment is wrapped oddly (you can go out to 80 characters), please rewrap. Also, it should end with a period.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10775
+
+    // We need use 32-bit subregister to avoid
+    // mismatch register class in 64-bit mode
----------------
Same as above.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D56077/new/

https://reviews.llvm.org/D56077