[PATCH] D54016: [X86] don't allow X86_64 PIC mode addresses to be used as immediates

[Yeoul Na via Phabricator via llvm-commits]

rapidsna updated this revision to Diff 179500.
rapidsna added a comment.
Herald added a subscriber: eraman.

Thanks for looking into this. I am adding a unit test for this patch.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54016/new/

https://reviews.llvm.org/D54016

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/inline-asm-pic-imm.ll


Index: test/CodeGen/X86/inline-asm-pic-imm.ll
===================================================================
--- test/CodeGen/X86/inline-asm-pic-imm.ll
+++ test/CodeGen/X86/inline-asm-pic-imm.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux -relocation-model=pic | FileCheck %s
+
+; Function Attrs: nounwind uwtable
+define void @_Z3foov() local_unnamed_addr #0 {
+entry:
+  tail call void asm sideeffect "movq $0,%gs:($1)", "ir,r,~{dirflag},~{fpsr},~{flags}"(i8* bitcast (void ()* @_ZL4foo2v to i8*), i32 0) #1
+  ret void
+; CHECK:    leaq  _ZL4foo2v(%rip), %rax
+; CHECK:    movq  %rax, %gs:(%ecx)
+}
+
+; Function Attrs: nounwind uwtable
+define internal void @_ZL4foo2v() #0 {
+entry:
+  ret void
+}
+
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -41983,7 +41983,8 @@
     // In any sort of PIC mode addresses need to be computed at runtime by
     // adding in a register or some sort of table lookup.  These can't
     // be used as immediates.
-    if (Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC())
+    if (Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC() ||
+        Subtarget.isPICStyleRIPRel())
       return;
 
     // If we are in non-pic codegen mode, we allow the address of a global (with


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