[llvm] r349880 - AMDGPU/GlobalISel: RegBankSelect for some fp ops
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 20 19:14:45 PST 2018
Author: arsenm
Date: Thu Dec 20 19:14:45 2018
New Revision: 349880
URL: http://llvm.org/viewvc/llvm-project?rev=349880&view=rev
Log:
AMDGPU/GlobalISel: RegBankSelect for some fp ops
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-round.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=349880&r1=349879&r2=349880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Dec 20 19:14:45 2018
@@ -161,6 +161,13 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
setAction({G_FPTOUI, S32}, Legal);
setAction({G_FPTOUI, 1, S32}, Legal);
+ setAction({G_FPOW, S32}, Legal);
+ setAction({G_FEXP2, S32}, Legal);
+ setAction({G_FLOG2, S32}, Legal);
+
+ getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
+ .legalFor({S32, S64});
+
for (LLT PtrTy : AddrSpaces) {
LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
setAction({G_GEP, PtrTy}, Legal);
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=349880&r1=349879&r2=349880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Thu Dec 20 19:14:45 2018
@@ -388,6 +388,10 @@ AMDGPURegisterBankInfo::getInstrMapping(
case AMDGPU::G_SITOFP:
case AMDGPU::G_UITOFP:
case AMDGPU::G_FPTRUNC:
+ case AMDGPU::G_FEXP2:
+ case AMDGPU::G_FLOG2:
+ case AMDGPU::G_INTRINSIC_TRUNC:
+ case AMDGPU::G_INTRINSIC_ROUND:
return getDefaultMappingVOP(MI);
case AMDGPU::G_IMPLICIT_DEF: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir?rev=349880&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir Thu Dec 20 19:14:45 2018
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_intrinsic_round_f32
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_intrinsic_round_f32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_INTRINSIC_ROUND %0
+...
+---
+name: test_intrinsic_round_f64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_intrinsic_round_f64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_INTRINSIC_ROUND %0
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir?rev=349880&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir Thu Dec 20 19:14:45 2018
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_intrinsic_trunc_f32
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_intrinsic_trunc_f32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_INTRINSIC_TRUNC %0
+...
+---
+name: test_intrinsic_trunc_f64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_intrinsic_trunc_f64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_INTRINSIC_TRUNC %0
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir?rev=349880&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir Thu Dec 20 19:14:45 2018
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: fexp2_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: fexp2_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[FEXP2_:%[0-9]+]]:vgpr(s32) = G_FEXP2 [[COPY]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FEXP2 %0
+...
+
+---
+name: fexp2_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: fexp2_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[FEXP2_:%[0-9]+]]:vgpr(s32) = G_FEXP2 [[COPY]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_FEXP2 %0
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir?rev=349880&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir Thu Dec 20 19:14:45 2018
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: flog2_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: flog2_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[FLOG2_:%[0-9]+]]:vgpr(s32) = G_FLOG2 [[COPY]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FLOG2 %0
+...
+
+---
+name: flog2_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: flog2_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[FLOG2_:%[0-9]+]]:vgpr(s32) = G_FLOG2 [[COPY]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_FLOG2 %0
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-round.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-round.mir?rev=349880&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-round.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-round.mir Thu Dec 20 19:14:45 2018
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: intrinsic_round_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: intrinsic_round_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_ROUND [[COPY]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_INTRINSIC_ROUND %0
+...
+
+---
+name: intrinsic_round_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: intrinsic_round_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_ROUND [[COPY]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_INTRINSIC_ROUND %0
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir?rev=349880&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir Thu Dec 20 19:14:45 2018
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: intrinsic_trunc_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: intrinsic_trunc_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_INTRINSIC_TRUNC %0
+...
+
+---
+name: intrinsic_trunc_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: intrinsic_trunc_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_INTRINSIC_TRUNC %0
+...
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