[PATCH] D55977: [PowerPC] Fix the bug of ISD::ADDE to set its second return type to glue

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
ZhangKang added reviewers: nemanjai, jsji, echristo, steven.zhang, hfinkel.

This patch is to fix the bug imported by rL341634 <https://reviews.llvm.org/rL341634>: https://reviews.llvm.org/rL341634 .
In above submit , the the return type of `ISD::ADDE` is `14224: SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64)`, 
but in fact, the second return type of `ISD::ADDE` should be `MVT::Glue` not `MVT::i64`.


https://reviews.llvm.org/D55977

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/adde_return_type.ll


Index: llvm/test/CodeGen/PowerPC/adde_return_type.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/adde_return_type.ll
@@ -0,0 +1,11 @@
+; REQUIRES: asserts
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -debug-only=legalize-types \
+; RUN:   < %s -o /dev/null 2>&1 | FileCheck %s
+
+define i64 @testAddeReturnType(i64 %X, i64 %Z) {
+; CHECK: Legally typed node: {{.*}}: i64,glue = adde {{.*}} 
+  %cmp = icmp ne i64 %Z, 0
+  %conv1 = zext i1 %cmp to i64
+  %add = add nsw i64 %conv1, %X
+  ret i64 %add
+}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14392,7 +14392,7 @@
     return SDValue();
 
   SDLoc DL(N);
-  SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64);
+  SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue);
   SDValue Cmp = RHS.getOperand(0);
   SDValue Z = Cmp.getOperand(0);
   auto *Constant = dyn_cast<ConstantSDNode>(Cmp.getOperand(1));


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