[PATCH] D55909: [ARMISelLowering] Recompute liveins after introducing new MBBs.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

The interesting constraint here is that ExpandISelPesudos runs immediately after ISel.  And if you have an instruction which produces physical registers from an allocatable register class, ISel will COPY the values to virtual registers immediately after that instruction (and similarly for instructions that consume physical registers).  So in practice, on ARM, the only physical register with a non-trivial live interval in ExpandISelPesudos is CPSR.

Granted, that's a bit fragile, and it isn't formally enforced anywhere.


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  https://reviews.llvm.org/D55909/new/

https://reviews.llvm.org/D55909