[PATCH] D41174: [X86][AVX512F_SCALAR]: Adding full coverage of MC encoding for the AVX512F_SCALAR isa sets.<NFC>

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: test/MC/X86/AVX512F_SCALAR-32.s:4
+// CHECK: vaddsd -485498096(%edx,%eax,4), %xmm1, %xmm1 
+// CHECK: encoding: [0xc5,0xf3,0x58,0x8c,0x82,0x10,0xe3,0x0f,0xe3]      
+vaddsd -485498096(%edx,%eax,4), %xmm1, %xmm1 
----------------
craig.topper wrote:
> This is a VEX encoding so this is testing AVX1. Not sure how to trick 32-bit mode to use EVEX for the unmasked instructions since you can't use the extended registers.
I don't know how to fix this without introducing support for the {evex} pseudo prefix that gas supports. But that's a bigger effort which I'm not even sure how to implement in the assembler implementation.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D41174/new/

https://reviews.llvm.org/D41174