[PATCH] D55722: [DAGCombiner] scalarize binop followed by extractelement

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: test/CodeGen/ARM/vector-promotion.ll:16
+; ASM: orr r0, r0, #1
+; ASM-NEXT: str r0, [r1]
 ; ASM-NEXT: bx
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This is destroying the whole point of the test: we want to avoid the expensive float->int register transfer.


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Comment at: test/CodeGen/ARM/vector-promotion.ll:87
 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
-; ASM-NOT: vmov.32 {{r[0-9]+}}, [[LOAD]]
+; ASM: mov.32	[[R:r[0-9]+]], [[LOAD]]
+; ASM: orr	[[R]], [[R]], #1
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Same here; this is destroying the point of the test.


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Comment at: test/CodeGen/ARM/vector-promotion.ll:394
+; ASM-NEXT:  str	[[LOAD]], [r1]
+; ASM-NEXT:  bx
 define void @simpleOneInstructionPromotion4x32(<4 x i32>* %addr1, i32* %dest) {
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This transform is okay, but I'd like to see a new test replacing the load with an intrinsic that produces a vector, to preserve the original intent.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55722/new/

https://reviews.llvm.org/D55722