[llvm] r349724 - [WebAssembly] Emit a splat for v128 IMPLICIT_DEF
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 19 20:20:33 PST 2018
Author: tlively
Date: Wed Dec 19 20:20:32 2018
New Revision: 349724
URL: http://llvm.org/viewvc/llvm-project?rev=349724&view=rev
Log:
[WebAssembly] Emit a splat for v128 IMPLICIT_DEF
Summary:
This is a code size savings and is also important to get runnable code
while engines do not support v128.const.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D55910
Modified:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
llvm/trunk/test/CodeGen/WebAssembly/implicit-def.ll
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp?rev=349724&r1=349723&r2=349724&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp Wed Dec 19 20:20:32 2018
@@ -98,7 +98,8 @@ static void ImposeStackOrdering(MachineI
static void ConvertImplicitDefToConstZero(MachineInstr *MI,
MachineRegisterInfo &MRI,
const TargetInstrInfo *TII,
- MachineFunction &MF) {
+ MachineFunction &MF,
+ LiveIntervals &LIS) {
assert(MI->getOpcode() == TargetOpcode::IMPLICIT_DEF);
const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
@@ -119,10 +120,13 @@ static void ConvertImplicitDefToConstZer
Type::getDoubleTy(MF.getFunction().getContext())));
MI->addOperand(MachineOperand::CreateFPImm(Val));
} else if (RegClass == &WebAssembly::V128RegClass) {
- // TODO: make splat instead of constant
- MI->setDesc(TII->get(WebAssembly::CONST_V128_v16i8));
- for (int I = 0; I < 16; ++I)
- MI->addOperand(MachineOperand::CreateImm(0));
+ unsigned TempReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
+ MI->setDesc(TII->get(WebAssembly::SPLAT_v4i32));
+ MI->addOperand(MachineOperand::CreateReg(TempReg, false));
+ MachineInstr *Const = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
+ TII->get(WebAssembly::CONST_I32), TempReg)
+ .addImm(0);
+ LIS.InsertMachineInstrInMaps(*Const);
} else {
llvm_unreachable("Unexpected reg class");
}
@@ -895,7 +899,7 @@ bool WebAssemblyRegStackify::runOnMachin
// to a constant 0 so that the def is explicit, and the push/pop
// correspondence is maintained.
if (Insert->getOpcode() == TargetOpcode::IMPLICIT_DEF)
- ConvertImplicitDefToConstZero(Insert, MRI, TII, MF);
+ ConvertImplicitDefToConstZero(Insert, MRI, TII, MF, LIS);
// We stackified an operand. Add the defining instruction's operands to
// the worklist stack now to continue to build an ever deeper tree.
Modified: llvm/trunk/test/CodeGen/WebAssembly/implicit-def.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/implicit-def.ll?rev=349724&r1=349723&r2=349724&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/implicit-def.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/implicit-def.ll Wed Dec 19 20:20:32 2018
@@ -109,8 +109,8 @@ X:
; CHECK-LABEL: implicit_def_v4i32:
; CHECK: .LBB{{[0-9]+}}_4:{{$}}
; CHECK-NEXT: end_block{{$}}
-; CHECK-NEXT: v128.const $push[[R:[0-9]+]]=, 0, 0, 0, 0, 0, 0, 0, 0,
-; CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0{{$}}
+; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; CHECK-NEXT: i32x4.splat $push[[R:[0-9]+]]=, $pop[[L0]]
; CHECK-NEXT: return $pop[[R]]{{$}}
; CHECK-NEXT: end_function{{$}}
define <4 x i32> @implicit_def_v4i32() {
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