[llvm] r349652 - [AArch64] Improve the Exynos M3 pipeline model

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Wed Dec 19 09:37:51 2018
New Revision: 349652

URL: http://llvm.org/viewvc/llvm-project?rev=349652&view=rev
Log:
[AArch64] Improve the Exynos M3 pipeline model

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
    llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=349652&r1=349651&r2=349652&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Wed Dec 19 09:37:51 2018
@@ -162,8 +162,8 @@ def M3WriteLE : SchedWriteRes<[M3UnitA,
                                            let NumMicroOps = 2; }
 def M3WriteLH : SchedWriteRes<[]>        { let Latency = 5;
                                            let NumMicroOps = 0; }
-def M3WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M3WriteL5]>,
-                                   SchedVar<NoSchedPred,   [M3WriteL4]>]>;
+def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
+                                   SchedVar<NoSchedPred,         [M3WriteL4]>]>;
 
 def M3WriteS1 : SchedWriteRes<[M3UnitS]>   { let Latency = 1; }
 def M3WriteSA : SchedWriteRes<[M3UnitA,
@@ -174,8 +174,8 @@ def M3WriteSB : SchedWriteRes<[M3UnitA,
                                M3UnitS]>   { let Latency = 2;
                                              let NumMicroOps = 2; }
 
-def M3ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
-                                      SchedVar<NoSchedPred,   [ReadDefault]>]>;
+def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
+                                      SchedVar<NoSchedPred,         [ReadDefault]>]>;
 
 // Branch instructions.
 def : SchedAlias<WriteBr, M3WriteZ0>;

Modified: llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s?rev=349652&r1=349651&r2=349652&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s (original)
+++ llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s Wed Dec 19 09:37:51 2018
@@ -50,7 +50,7 @@
 # EM1-NEXT:  1      5     1.00    *                   ldr	d21, [x22, x23, lsl #3]
 # EM1-NEXT:  2      6     2.00    *                   ldr	q24, [x25, x26, lsl #4]
 
-# EM3-NEXT:  1      5     0.50    *                   ldrb	w0, [x1, x2, lsl #0]
+# EM3-NEXT:  1      4     0.50    *                   ldrb	w0, [x1, x2, lsl #0]
 # EM3-NEXT:  1      5     0.50    *                   ldrh	w3, [x4, x5, sxtx #1]
 # EM3-NEXT:  2      5     0.50    *                   ldr	w6, [x7, w8, uxtw #2]
 # EM3-NEXT:  2      5     0.50    *                   ldr	x9, [x10, w11, sxtw #3]