[llvm] r349616 - [SelectionDAG] Optional handling of UNDEF elements in matchUnaryPredicate
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 19 02:41:06 PST 2018
Author: rksimon
Date: Wed Dec 19 02:41:06 2018
New Revision: 349616
URL: http://llvm.org/viewvc/llvm-project?rev=349616&view=rev
Log:
[SelectionDAG] Optional handling of UNDEF elements in matchUnaryPredicate
Now that SimplifyDemandedBits/SimplifyDemandedVectorElts are simplifying vector elements, we're seeing more constant BUILD_VECTOR containing UNDEFs.
This patch provides opt-in handling of UNDEF elements in matchUnaryPredicate, passing NULL instead of the ConstantSDNode* argument.
I've updated SelectionDAG::simplifyShift to demonstrate its use.
Differential Revision: https://reviews.llvm.org/D55819
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/test/CodeGen/X86/combine-shl.ll
llvm/trunk/test/CodeGen/X86/combine-sra.ll
llvm/trunk/test/CodeGen/X86/combine-srl.ll
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=349616&r1=349615&r2=349616&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Dec 19 02:41:06 2018
@@ -2487,8 +2487,10 @@ namespace ISD {
/// Attempt to match a unary predicate against a scalar/splat constant or
/// every element of a constant BUILD_VECTOR.
+ /// If AllowUndef is true, then UNDEF element will pass nullptr to Match.
bool matchUnaryPredicate(SDValue Op,
- std::function<bool(ConstantSDNode *)> Match);
+ std::function<bool(ConstantSDNode *)> Match,
+ bool AllowUndefs = false);
/// Attempt to match a binary predicate against a pair of scalar/splat
/// constants or every element of a pair of constant BUILD_VECTORs.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=349616&r1=349615&r2=349616&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Dec 19 02:41:06 2018
@@ -269,15 +269,24 @@ bool ISD::allOperandsUndef(const SDNode
}
bool ISD::matchUnaryPredicate(SDValue Op,
- std::function<bool(ConstantSDNode *)> Match) {
+ std::function<bool(ConstantSDNode *)> Match,
+ bool AllowUndefs) {
+ // FIXME: Add support for scalar UNDEF cases?
if (auto *Cst = dyn_cast<ConstantSDNode>(Op))
return Match(Cst);
+ // FIXME: Add support for vector UNDEF cases?
if (ISD::BUILD_VECTOR != Op.getOpcode())
return false;
EVT SVT = Op.getValueType().getScalarType();
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
+ if (AllowUndefs && Op.getOperand(i).isUndef()) {
+ if (!Match(nullptr))
+ return false;
+ continue;
+ }
+
auto *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(i));
if (!Cst || Cst->getValueType(0) != SVT || !Match(Cst))
return false;
@@ -6967,11 +6976,11 @@ SDValue SelectionDAG::simplifyShift(SDVa
return X;
// shift X, C >= bitwidth(X) --> undef
- // All vector elements must be too big to avoid partial undefs.
+ // All vector elements must be too big (or undef) to avoid partial undefs.
auto isShiftTooBig = [X](ConstantSDNode *Val) {
- return Val->getAPIntValue().uge(X.getScalarValueSizeInBits());
+ return !Val || Val->getAPIntValue().uge(X.getScalarValueSizeInBits());
};
- if (ISD::matchUnaryPredicate(Y, isShiftTooBig))
+ if (ISD::matchUnaryPredicate(Y, isShiftTooBig, true))
return getUNDEF(X.getValueType());
return SDValue();
Modified: llvm/trunk/test/CodeGen/X86/combine-shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-shl.ll?rev=349616&r1=349615&r2=349616&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-shl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-shl.ll Wed Dec 19 02:41:06 2018
@@ -46,15 +46,9 @@ define <4 x i32> @combine_vec_shl_outofr
}
define <4 x i32> @combine_vec_shl_outofrange3(<4 x i32> %a0) {
-; SSE-LABEL: combine_vec_shl_outofrange3:
-; SSE: # %bb.0:
-; SSE-NEXT: xorps %xmm0, %xmm0
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_shl_outofrange3:
-; AVX: # %bb.0:
-; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_shl_outofrange3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = shl <4 x i32> %a0, <i32 33, i32 34, i32 35, i32 undef>
ret <4 x i32> %1
}
Modified: llvm/trunk/test/CodeGen/X86/combine-sra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sra.ll?rev=349616&r1=349615&r2=349616&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sra.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sra.ll Wed Dec 19 02:41:06 2018
@@ -51,14 +51,9 @@ define <4 x i32> @combine_vec_ashr_outof
}
define <4 x i32> @combine_vec_ashr_outofrange2(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_ashr_outofrange2:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_ashr_outofrange2:
-; AVX: # %bb.0:
-; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_ashr_outofrange2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 undef>
ret <4 x i32> %1
}
Modified: llvm/trunk/test/CodeGen/X86/combine-srl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srl.ll?rev=349616&r1=349615&r2=349616&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srl.ll Wed Dec 19 02:41:06 2018
@@ -36,14 +36,9 @@ define <4 x i32> @combine_vec_lshr_outof
}
define <4 x i32> @combine_vec_lshr_outofrange2(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_lshr_outofrange2:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_lshr_outofrange2:
-; AVX: # %bb.0:
-; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_lshr_outofrange2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 undef>
ret <4 x i32> %1
}
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