[PATCH] D55871: AMDGPU/GlobalISel: Disallow VGPR->SCC copies

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellar.
Herald added subscribers: t-tye, tpr, dstuttard, kristof.beyls, rovka, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

This fixes using scalar adds when only the carry in is a VGPR
using greedy regbankselect.


https://reviews.llvm.org/D55871

Files:
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir


Index: test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
+++ test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
@@ -84,8 +84,10 @@
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
-    ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
-    ; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
+    ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+    ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+    ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+    ; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $vgpr0
Index: test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
+++ test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
@@ -83,8 +83,10 @@
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
-    ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
-    ; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
+    ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+    ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+    ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+    ; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $vgpr0
Index: test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
+++ test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
@@ -84,8 +84,10 @@
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
-    ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
-    ; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
+    ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+    ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+    ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+    ; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $vgpr0
Index: test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
+++ test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
@@ -84,8 +84,10 @@
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
-    ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
-    ; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
+    ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+    ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+    ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+    ; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $vgpr0
Index: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -74,13 +74,19 @@
                                           const RegisterBank &Src,
                                           unsigned Size) const {
   if (Dst.getID() == AMDGPU::SGPRRegBankID &&
-      Src.getID() == AMDGPU::VGPRRegBankID)
+      Src.getID() == AMDGPU::VGPRRegBankID) {
+    // For boolean values, we can do a v_cmp to "copy" a VGPR to VCC.
+    if (Size == 1)
+      return 1;
+
     return std::numeric_limits<unsigned>::max();
+  }
 
   // SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
   // the valu.
   if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
-      Src.getID() == AMDGPU::SGPRRegBankID)
+      (Src.getID() == AMDGPU::SGPRRegBankID ||
+       Src.getID() == AMDGPU::VGPRRegBankID))
     return std::numeric_limits<unsigned>::max();
 
   return RegisterBankInfo::copyCost(Dst, Src, Size);


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