[llvm] r349483 - [X86][SSE] Add shift combine 'out of range' tests with UNDEFs

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Dec 18 05:37:04 2018
New Revision: 349483

URL: http://llvm.org/viewvc/llvm-project?rev=349483&view=rev
Log:
[X86][SSE] Add shift combine 'out of range' tests with UNDEFs

Shows failure to simplify out of range shift amounts to UNDEF if any element is UNDEF.

Modified:
    llvm/trunk/test/CodeGen/X86/combine-shl.ll
    llvm/trunk/test/CodeGen/X86/combine-sra.ll
    llvm/trunk/test/CodeGen/X86/combine-srl.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-shl.ll?rev=349483&r1=349482&r2=349483&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-shl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-shl.ll Tue Dec 18 05:37:04 2018
@@ -45,6 +45,20 @@ define <4 x i32> @combine_vec_shl_outofr
   ret <4 x i32> %2
 }
 
+define <4 x i32> @combine_vec_shl_outofrange3(<4 x i32> %a0) {
+; SSE-LABEL: combine_vec_shl_outofrange3:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_shl_outofrange3:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = shl <4 x i32> %a0, <i32 33, i32 34, i32 35, i32 undef>
+  ret <4 x i32> %1
+}
+
 ; fold (shl x, 0) -> x
 define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) {
 ; CHECK-LABEL: combine_vec_shl_by_zero:

Modified: llvm/trunk/test/CodeGen/X86/combine-sra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sra.ll?rev=349483&r1=349482&r2=349483&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sra.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sra.ll Tue Dec 18 05:37:04 2018
@@ -50,6 +50,19 @@ define <4 x i32> @combine_vec_ashr_outof
   ret <4 x i32> %1
 }
 
+define <4 x i32> @combine_vec_ashr_outofrange2(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_ashr_outofrange2:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_ashr_outofrange2:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsravd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = ashr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 undef>
+  ret <4 x i32> %1
+}
+
 ; fold (sra x, 0) -> x
 define <4 x i32> @combine_vec_ashr_by_zero(<4 x i32> %x) {
 ; CHECK-LABEL: combine_vec_ashr_by_zero:

Modified: llvm/trunk/test/CodeGen/X86/combine-srl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srl.ll?rev=349483&r1=349482&r2=349483&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srl.ll Tue Dec 18 05:37:04 2018
@@ -35,6 +35,19 @@ define <4 x i32> @combine_vec_lshr_outof
   ret <4 x i32> %1
 }
 
+define <4 x i32> @combine_vec_lshr_outofrange2(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_lshr_outofrange2:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_lshr_outofrange2:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = lshr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 undef>
+  ret <4 x i32> %1
+}
+
 ; fold (srl x, 0) -> x
 define <4 x i32> @combine_vec_lshr_by_zero(<4 x i32> %x) {
 ; CHECK-LABEL: combine_vec_lshr_by_zero: