[llvm] r349468 - AMDGPU: Legalize/regbankselect frame_index
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 18 01:46:14 PST 2018
Author: arsenm
Date: Tue Dec 18 01:46:13 2018
New Revision: 349468
URL: http://llvm.org/viewvc/llvm-project?rev=349468&view=rev
Log:
AMDGPU: Legalize/regbankselect frame_index
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=349468&r1=349467&r2=349468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Tue Dec 18 01:46:13 2018
@@ -90,6 +90,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
// between these two scenarios.
setAction({G_CONSTANT, S1}, Legal);
+ setAction({G_FRAME_INDEX, PrivatePtr}, Legal);
+
getActionDefinitionsBuilder(
{ G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})
.legalFor({S32, S64});
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=349468&r1=349467&r2=349468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Tue Dec 18 01:46:13 2018
@@ -366,6 +366,7 @@ AMDGPURegisterBankInfo::getInstrMapping(
}
case AMDGPU::G_FCONSTANT:
case AMDGPU::G_CONSTANT:
+ case AMDGPU::G_FRAME_INDEX:
case AMDGPU::G_BLOCK_ADDR: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir?rev=349468&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir Tue Dec 18 01:46:13 2018
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+--- |
+ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+ define void @test_frame_index_p5() {
+ %ptr0 = alloca i32, addrspace(5)
+ ret void
+ }
+...
+---
+name: test_frame_index_p5
+legalized: true
+stack:
+ - { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_frame_index_p5
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:sgpr(p5) = G_FRAME_INDEX %stack.0.ptr0
+ %0:_(p5) = G_FRAME_INDEX %stack.0.ptr0
+
+...
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