[PATCH] D55809: GlobalISel: Verify g_zextload and g_sextload

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
Herald added subscribers: javed.absar, kristof.beyls, rovka, wdng.

https://reviews.llvm.org/D55809

Files:
  lib/CodeGen/MachineVerifier.cpp
  test/CodeGen/MIR/AArch64/invalid-extload.mir


Index: test/CodeGen/MIR/AArch64/invalid-extload.mir
===================================================================
--- /dev/null
+++ test/CodeGen/MIR/AArch64/invalid-extload.mir
@@ -0,0 +1,23 @@
+# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+
+---
+name: invalid_extload_memory_sizes
+body: |
+  bb.0:
+
+    %0:_(p0) = COPY $x0
+    %1:_(s64) = G_ZEXTLOAD %0(p0) :: (load 8)
+    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 16)
+    %3:_(s64) = G_SEXTLOAD %0(p0) :: (load 8)
+    %4:_(s64) = G_SEXTLOAD %0(p0) :: (load 16)
+    %5:_(s64) = G_ZEXTLOAD %0(p0)
+    %6:_(s64) = G_SEXTLOAD %0(p0)
+
+...
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -980,11 +980,24 @@
     break;
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
+  case TargetOpcode::G_ZEXTLOAD:
+  case TargetOpcode::G_SEXTLOAD:
     // Generic loads and stores must have a single MachineMemOperand
     // describing that access.
-    if (!MI->hasOneMemOperand())
+    if (!MI->hasOneMemOperand()) {
       report("Generic instruction accessing memory must have one mem operand",
              MI);
+    } else {
+      if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
+          MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
+        const MachineMemOperand &MMO = **MI->memoperands_begin();
+        LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+        if (MMO.getSize() * 8 >= DstTy.getSizeInBits()) {
+          report("Generic extload must have a narrower memory type", MI);
+        }
+      }
+    }
+
     break;
   case TargetOpcode::G_PHI: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());


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