[llvm] r349368 - [AMDGPU][MC][DOC] Updated AMD GPU assembler description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 17 09:38:13 PST 2018
Removed: llvm/trunk/docs/AMDGPUAsmGFX8.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUAsmGFX8.rst?rev=349367&view=auto
==============================================================================
--- llvm/trunk/docs/AMDGPUAsmGFX8.rst (original)
+++ llvm/trunk/docs/AMDGPUAsmGFX8.rst (removed)
@@ -1,1672 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-===========================
-Syntax of GFX8 Instructions
-===========================
-
-.. contents::
- :local:
-
-
-DS
-===========================
-
-.. parsed-literal::
-
- ds_add_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_append dst :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_bpermute_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
- ds_cmpst_b32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_b64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_condxchg32_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_consume dst :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_barrier src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_init src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_br src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_p :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_release_all :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_v :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_nop
- ds_or_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_ordered_count dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_permute_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
- ds_read2_b32 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2_b64 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b32 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b64 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b128 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b32 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b64 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b96 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_swizzle_b32 dst, src0 :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrap_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b32 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b64 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b32 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b64 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b128 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b16 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b8 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b96 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-
-EXP
-===========================
-
-.. parsed-literal::
-
- exp dst, src0, src1, src2, src3 :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
-
-FLAT
-===========================
-
-.. parsed-literal::
-
- flat_atomic_add dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_add_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dword dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx2 dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx3 dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx4 dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sbyte dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sshort dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ubyte dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ushort dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_byte src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dword src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx2 src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx3 src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx4 src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_short src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-
-MIMG
-===========================
-
-.. parsed-literal::
-
- image_atomic_add dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_and dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_cmpswap dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_dec dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_inc dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_or dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smax dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smin dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_sub dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_swap dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umax dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umin dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_xor dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4 dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_get_lod dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_get_resinfo dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip_pck dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_mip_pck_sgn dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck_sgn dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip_pck src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_store_pck src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-
-MUBUF
-===========================
-
-.. parsed-literal::
-
- buffer_atomic_add dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_add_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dword dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_dwordx2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx3 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx4 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_x dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xy dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xyz dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xyzw dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_x dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_format_xy dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyz dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyzw dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sbyte dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_sshort dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ushort dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_byte src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dword src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx2 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx3 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx4 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_x src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xy src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyz src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyzw src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_x src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xy src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyz src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyzw src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_lds_dword src0, src1 :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_wbinvl1
- buffer_wbinvl1_vol
-
-SMEM
-===========================
-
-.. parsed-literal::
-
- s_atc_probe src0, src1, src2
- s_atc_probe_buffer src0, src1, src2
- s_buffer_load_dword dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx16 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx4 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx8 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dword src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx2 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx4 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_dcache_inv
- s_dcache_inv_vol
- s_dcache_wb
- s_dcache_wb_vol
- s_load_dword dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx16 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx4 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx8 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_memrealtime dst
- s_memtime dst
- s_store_dword src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx2 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx4 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
-
-SOP1
-===========================
-
-.. parsed-literal::
-
- s_abs_i32 dst, src0
- s_and_saveexec_b64 dst, src0
- s_andn2_saveexec_b64 dst, src0
- s_bcnt0_i32_b32 dst, src0
- s_bcnt0_i32_b64 dst, src0
- s_bcnt1_i32_b32 dst, src0
- s_bcnt1_i32_b64 dst, src0
- s_bitset0_b32 dst, src0
- s_bitset0_b64 dst, src0
- s_bitset1_b32 dst, src0
- s_bitset1_b64 dst, src0
- s_brev_b32 dst, src0
- s_brev_b64 dst, src0
- s_cbranch_join src0
- s_cmov_b32 dst, src0
- s_cmov_b64 dst, src0
- s_ff0_i32_b32 dst, src0
- s_ff0_i32_b64 dst, src0
- s_ff1_i32_b32 dst, src0
- s_ff1_i32_b64 dst, src0
- s_flbit_i32 dst, src0
- s_flbit_i32_b32 dst, src0
- s_flbit_i32_b64 dst, src0
- s_flbit_i32_i64 dst, src0
- s_getpc_b64 dst
- s_mov_b32 dst, src0
- s_mov_b64 dst, src0
- s_mov_fed_b32 dst, src0
- s_movreld_b32 dst, src0
- s_movreld_b64 dst, src0
- s_movrels_b32 dst, src0
- s_movrels_b64 dst, src0
- s_nand_saveexec_b64 dst, src0
- s_nor_saveexec_b64 dst, src0
- s_not_b32 dst, src0
- s_not_b64 dst, src0
- s_or_saveexec_b64 dst, src0
- s_orn2_saveexec_b64 dst, src0
- s_quadmask_b32 dst, src0
- s_quadmask_b64 dst, src0
- s_rfe_b64 src0
- s_set_gpr_idx_idx src0
- s_setpc_b64 src0
- s_sext_i32_i16 dst, src0
- s_sext_i32_i8 dst, src0
- s_swappc_b64 dst, src0
- s_wqm_b32 dst, src0
- s_wqm_b64 dst, src0
- s_xnor_saveexec_b64 dst, src0
- s_xor_saveexec_b64 dst, src0
-
-SOP2
-===========================
-
-.. parsed-literal::
-
- s_absdiff_i32 dst, src0, src1
- s_add_i32 dst, src0, src1
- s_add_u32 dst, src0, src1
- s_addc_u32 dst, src0, src1
- s_and_b32 dst, src0, src1
- s_and_b64 dst, src0, src1
- s_andn2_b32 dst, src0, src1
- s_andn2_b64 dst, src0, src1
- s_ashr_i32 dst, src0, src1
- s_ashr_i64 dst, src0, src1
- s_bfe_i32 dst, src0, src1
- s_bfe_i64 dst, src0, src1
- s_bfe_u32 dst, src0, src1
- s_bfe_u64 dst, src0, src1
- s_bfm_b32 dst, src0, src1
- s_bfm_b64 dst, src0, src1
- s_cbranch_g_fork src0, src1
- s_cselect_b32 dst, src0, src1
- s_cselect_b64 dst, src0, src1
- s_lshl_b32 dst, src0, src1
- s_lshl_b64 dst, src0, src1
- s_lshr_b32 dst, src0, src1
- s_lshr_b64 dst, src0, src1
- s_max_i32 dst, src0, src1
- s_max_u32 dst, src0, src1
- s_min_i32 dst, src0, src1
- s_min_u32 dst, src0, src1
- s_mul_i32 dst, src0, src1
- s_nand_b32 dst, src0, src1
- s_nand_b64 dst, src0, src1
- s_nor_b32 dst, src0, src1
- s_nor_b64 dst, src0, src1
- s_or_b32 dst, src0, src1
- s_or_b64 dst, src0, src1
- s_orn2_b32 dst, src0, src1
- s_orn2_b64 dst, src0, src1
- s_rfe_restore_b64 src0, src1
- s_sub_i32 dst, src0, src1
- s_sub_u32 dst, src0, src1
- s_subb_u32 dst, src0, src1
- s_xnor_b32 dst, src0, src1
- s_xnor_b64 dst, src0, src1
- s_xor_b32 dst, src0, src1
- s_xor_b64 dst, src0, src1
-
-SOPC
-===========================
-
-.. parsed-literal::
-
- s_bitcmp0_b32 src0, src1
- s_bitcmp0_b64 src0, src1
- s_bitcmp1_b32 src0, src1
- s_bitcmp1_b64 src0, src1
- s_cmp_eq_i32 src0, src1
- s_cmp_eq_u32 src0, src1
- s_cmp_eq_u64 src0, src1
- s_cmp_ge_i32 src0, src1
- s_cmp_ge_u32 src0, src1
- s_cmp_gt_i32 src0, src1
- s_cmp_gt_u32 src0, src1
- s_cmp_le_i32 src0, src1
- s_cmp_le_u32 src0, src1
- s_cmp_lg_i32 src0, src1
- s_cmp_lg_u32 src0, src1
- s_cmp_lg_u64 src0, src1
- s_cmp_lt_i32 src0, src1
- s_cmp_lt_u32 src0, src1
- s_set_gpr_idx_on src0, src1
- s_setvskip src0, src1
-
-SOPK
-===========================
-
-.. parsed-literal::
-
- s_addk_i32 dst, src0
- s_cbranch_i_fork src0, src1
- s_cmovk_i32 dst, src0
- s_cmpk_eq_i32 src0, src1
- s_cmpk_eq_u32 src0, src1
- s_cmpk_ge_i32 src0, src1
- s_cmpk_ge_u32 src0, src1
- s_cmpk_gt_i32 src0, src1
- s_cmpk_gt_u32 src0, src1
- s_cmpk_le_i32 src0, src1
- s_cmpk_le_u32 src0, src1
- s_cmpk_lg_i32 src0, src1
- s_cmpk_lg_u32 src0, src1
- s_cmpk_lt_i32 src0, src1
- s_cmpk_lt_u32 src0, src1
- s_getreg_b32 dst, src0
- s_movk_i32 dst, src0
- s_mulk_i32 dst, src0
- s_setreg_b32 dst, src0
- s_setreg_imm32_b32 dst, src0
-
-SOPP
-===========================
-
-.. parsed-literal::
-
- s_barrier
- s_branch src0
- s_cbranch_cdbgsys src0
- s_cbranch_cdbgsys_and_user src0
- s_cbranch_cdbgsys_or_user src0
- s_cbranch_cdbguser src0
- s_cbranch_execnz src0
- s_cbranch_execz src0
- s_cbranch_scc0 src0
- s_cbranch_scc1 src0
- s_cbranch_vccnz src0
- s_cbranch_vccz src0
- s_decperflevel src0
- s_endpgm
- s_endpgm_saved
- s_icache_inv
- s_incperflevel src0
- s_nop src0
- s_sendmsg src0
- s_sendmsghalt src0
- s_set_gpr_idx_mode src0
- s_set_gpr_idx_off
- s_sethalt src0
- s_setkill src0
- s_setprio src0
- s_sleep src0
- s_trap src0
- s_ttracedata
- s_waitcnt src0
- s_wakeup
-
-VINTRP
-===========================
-
-.. parsed-literal::
-
- v_interp_mov_f32 dst, src0, src1
- v_interp_p1_f32 dst, src0, src1
- v_interp_p2_f32 dst, src0, src1
-
-VOP1
-===========================
-
-.. parsed-literal::
-
- v_bfrev_b32 dst, src0
- v_bfrev_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_bfrev_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f16 dst, src0
- v_ceil_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ceil_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f32 dst, src0
- v_ceil_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ceil_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f64 dst, src0
- v_clrexcp
- v_cos_f16 dst, src0
- v_cos_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cos_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cos_f32 dst, src0
- v_cos_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cos_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_f32 dst, src0
- v_cvt_f16_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_i16 dst, src0
- v_cvt_f16_i16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_i16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_u16 dst, src0
- v_cvt_f16_u16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_u16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_f16 dst, src0
- v_cvt_f32_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_f64 dst, src0
- v_cvt_f32_i32 dst, src0
- v_cvt_f32_i32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_i32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_u32 dst, src0
- v_cvt_f32_u32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_u32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte0 dst, src0
- v_cvt_f32_ubyte0_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte0_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte1 dst, src0
- v_cvt_f32_ubyte1_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte1_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte2 dst, src0
- v_cvt_f32_ubyte2_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte2_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte3 dst, src0
- v_cvt_f32_ubyte3_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte3_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f64_f32 dst, src0
- v_cvt_f64_i32 dst, src0
- v_cvt_f64_u32 dst, src0
- v_cvt_flr_i32_f32 dst, src0
- v_cvt_flr_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_flr_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i16_f16 dst, src0
- v_cvt_i16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_i16_f16_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i32_f32 dst, src0
- v_cvt_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i32_f64 dst, src0
- v_cvt_off_f32_i4 dst, src0
- v_cvt_off_f32_i4_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_off_f32_i4_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_rpi_i32_f32 dst, src0
- v_cvt_rpi_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_rpi_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u16_f16 dst, src0
- v_cvt_u16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_u16_f16_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u32_f32 dst, src0
- v_cvt_u32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_u32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u32_f64 dst, src0
- v_exp_f16 dst, src0
- v_exp_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_f32 dst, src0
- v_exp_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_legacy_f32 dst, src0
- v_exp_legacy_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_legacy_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_i32 dst, src0
- v_ffbh_i32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbh_i32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_u32 dst, src0
- v_ffbh_u32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbh_u32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbl_b32 dst, src0
- v_ffbl_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbl_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f16 dst, src0
- v_floor_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_floor_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f32 dst, src0
- v_floor_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_floor_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f64 dst, src0
- v_fract_f16 dst, src0
- v_fract_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_fract_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f32 dst, src0
- v_fract_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_fract_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f64 dst, src0
- v_frexp_exp_i16_f16 dst, src0
- v_frexp_exp_i16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_exp_i16_f16_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i32_f32 dst, src0
- v_frexp_exp_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_exp_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i32_f64 dst, src0
- v_frexp_mant_f16 dst, src0
- v_frexp_mant_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_mant_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f32 dst, src0
- v_frexp_mant_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_mant_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f64 dst, src0
- v_log_f16 dst, src0
- v_log_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_log_f32 dst, src0
- v_log_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_log_legacy_f32 dst, src0
- v_log_legacy_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_legacy_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_mov_b32 dst, src0
- v_mov_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mov_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_mov_fed_b32 dst, src0
- v_mov_fed_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mov_fed_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_movreld_b32 dst, src0
- v_movrels_b32 dst, src0
- v_movrelsd_b32 dst, src0
- v_nop
- v_not_b32 dst, src0
- v_not_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_not_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f16 dst, src0
- v_rcp_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f32 dst, src0
- v_rcp_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f64 dst, src0
- v_rcp_iflag_f32 dst, src0
- v_rcp_iflag_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_iflag_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_readfirstlane_b32 dst, src0
- v_rndne_f16 dst, src0
- v_rndne_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rndne_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f32 dst, src0
- v_rndne_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rndne_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f64 dst, src0
- v_rsq_f16 dst, src0
- v_rsq_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rsq_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f32 dst, src0
- v_rsq_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rsq_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f64 dst, src0
- v_sin_f16 dst, src0
- v_sin_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sin_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sin_f32 dst, src0
- v_sin_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sin_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f16 dst, src0
- v_sqrt_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sqrt_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f32 dst, src0
- v_sqrt_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sqrt_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f64 dst, src0
- v_trunc_f16 dst, src0
- v_trunc_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_trunc_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_trunc_f32 dst, src0
- v_trunc_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_trunc_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_trunc_f64 dst, src0
-
-VOP2
-===========================
-
-.. parsed-literal::
-
- v_add_f16 dst, src0, src1
- v_add_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_f32 dst, src0, src1
- v_add_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_u16 dst, src0, src1
- v_add_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_u32 dst0, dst1, src0, src1
- v_add_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_addc_u32 dst0, dst1, src0, src1, src2
- v_addc_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_addc_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_and_b32 dst, src0, src1
- v_and_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_and_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i16 dst, src0, src1
- v_ashrrev_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i32 dst, src0, src1
- v_ashrrev_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cndmask_b32 dst, src0, src1, src2
- v_cndmask_b32_dpp dst, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cndmask_b32_sdwa dst, src0, src1, src2 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ldexp_f16 dst, src0, src1
- v_ldexp_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ldexp_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b16 dst, src0, src1
- v_lshlrev_b16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b32 dst, src0, src1
- v_lshlrev_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b16 dst, src0, src1
- v_lshrrev_b16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b32 dst, src0, src1
- v_lshrrev_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mac_f16 dst, src0, src1
- v_mac_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mac_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mac_f32 dst, src0, src1
- v_mac_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mac_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_madak_f16 dst, src0, src1, src2
- v_madak_f32 dst, src0, src1, src2
- v_madmk_f16 dst, src0, src1, src2
- v_madmk_f32 dst, src0, src1, src2
- v_max_f16 dst, src0, src1
- v_max_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_f32 dst, src0, src1
- v_max_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_i16 dst, src0, src1
- v_max_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_i16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_i32 dst, src0, src1
- v_max_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_i32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_u16 dst, src0, src1
- v_max_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_u16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_u32 dst, src0, src1
- v_max_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_u32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f16 dst, src0, src1
- v_min_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f32 dst, src0, src1
- v_min_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_i16 dst, src0, src1
- v_min_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_i16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_i32 dst, src0, src1
- v_min_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_i32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_u16 dst, src0, src1
- v_min_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_u16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_u32 dst, src0, src1
- v_min_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_u32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_f16 dst, src0, src1
- v_mul_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_f32 dst, src0, src1
- v_mul_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_i32_i24 dst, src0, src1
- v_mul_hi_i32_i24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_hi_i32_i24_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_u32_u24 dst, src0, src1
- v_mul_hi_u32_u24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_hi_u32_u24_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_i32_i24 dst, src0, src1
- v_mul_i32_i24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_i32_i24_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_legacy_f32 dst, src0, src1
- v_mul_legacy_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_legacy_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_lo_u16 dst, src0, src1
- v_mul_lo_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_lo_u16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_u32_u24 dst, src0, src1
- v_mul_u32_u24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_u32_u24_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_or_b32 dst, src0, src1
- v_or_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_or_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f16 dst, src0, src1
- v_sub_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f32 dst, src0, src1
- v_sub_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_u16 dst, src0, src1
- v_sub_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_u32 dst0, dst1, src0, src1
- v_sub_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subb_u32 dst0, dst1, src0, src1, src2
- v_subb_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subb_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subbrev_u32 dst0, dst1, src0, src1, src2
- v_subbrev_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subbrev_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f16 dst, src0, src1
- v_subrev_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f32 dst, src0, src1
- v_subrev_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u16 dst, src0, src1
- v_subrev_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u32 dst0, dst1, src0, src1
- v_subrev_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_xor_b32 dst, src0, src1
- v_xor_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_xor_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-
-VOP3
-===========================
-
-.. parsed-literal::
-
- v_add_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_add_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_addc_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_alignbit_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_alignbyte_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_and_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_ashrrev_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_ashrrev_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_ashrrev_i64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_bcnt_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_bfe_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_bfe_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_bfi_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_bfm_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_bfrev_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_clrexcp_e64 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_class_f16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_class_f32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_class_f64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_neq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_neq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_neq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ngt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ngt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ngt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nle_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nle_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nle_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_o_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_o_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_o_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_tru_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_tru_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_tru_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_u_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_u_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_u_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_class_f16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_class_f32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_class_f64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_neq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_neq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_neq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ngt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ngt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ngt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nle_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nle_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nle_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_o_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_o_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_o_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_tru_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_tru_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_tru_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_u_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_u_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_u_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cndmask_b32_e64 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_cos_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cos_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubeid_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubema_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubesc_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubetc_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_i16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_u16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_i32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_u32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte0_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte1_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte2_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte3_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_i32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_u32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_flr_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_i16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_i32_f64_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_off_f32_i4_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_i16_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_u16_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_u8_f32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pkaccum_u8_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pknorm_i16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pknorm_u16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pkrtz_f16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_rpi_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_u16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_u32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_u32_f64_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f32 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_exp_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_legacy_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_i32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_u32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_ffbl_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_floor_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_floor_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_floor_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i32_f64_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_mov_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1ll_f16 dst, src0, src1 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1lv_f16 dst, src0, src1, src2 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_f16 dst, src0, src1, src2 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f32 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lerp_u8 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_log_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_legacy_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lshlrev_b16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshlrev_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshlrev_b64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshrrev_b16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshrrev_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshrrev_b64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mac_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mac_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i32_i24 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i64_i32 dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_legacy_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u32_u24 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u64_u32 dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_max3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_max_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_max_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_max_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_max_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mbcnt_hi_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mbcnt_lo_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_med3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_med3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_min3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_min3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_min_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_min_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_min_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_min_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mov_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_mov_fed_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_movreld_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_movrels_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_movrelsd_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_mqsad_pk_u16_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mqsad_u32_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_msad_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32_i24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_u32_u24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_i32_i24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_legacy_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_u32_u24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_nop_e64 :ref:`omod<amdgpu_synid_omod>`
- v_not_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_or_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_perm_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_qsad_pk_u16_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_iflag_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_readlane_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_hi_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_u16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_u32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sin_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sin_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_sub_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_subb_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_subbrev_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_subrev_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_subrev_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_trig_preop_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_writelane_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_xor_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
-
-VOPC
-===========================
-
-.. parsed-literal::
-
- v_cmp_class_f16 dst, src0, src1
- v_cmp_class_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_class_f32 dst, src0, src1
- v_cmp_class_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_class_f64 dst, src0, src1
- v_cmp_eq_f16 dst, src0, src1
- v_cmp_eq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f32 dst, src0, src1
- v_cmp_eq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f64 dst, src0, src1
- v_cmp_eq_i16 dst, src0, src1
- v_cmp_eq_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i32 dst, src0, src1
- v_cmp_eq_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i64 dst, src0, src1
- v_cmp_eq_u16 dst, src0, src1
- v_cmp_eq_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u32 dst, src0, src1
- v_cmp_eq_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u64 dst, src0, src1
- v_cmp_f_f16 dst, src0, src1
- v_cmp_f_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f32 dst, src0, src1
- v_cmp_f_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f64 dst, src0, src1
- v_cmp_f_i16 dst, src0, src1
- v_cmp_f_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_i32 dst, src0, src1
- v_cmp_f_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_i64 dst, src0, src1
- v_cmp_f_u16 dst, src0, src1
- v_cmp_f_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_u32 dst, src0, src1
- v_cmp_f_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_u64 dst, src0, src1
- v_cmp_ge_f16 dst, src0, src1
- v_cmp_ge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f32 dst, src0, src1
- v_cmp_ge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f64 dst, src0, src1
- v_cmp_ge_i16 dst, src0, src1
- v_cmp_ge_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i32 dst, src0, src1
- v_cmp_ge_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i64 dst, src0, src1
- v_cmp_ge_u16 dst, src0, src1
- v_cmp_ge_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u32 dst, src0, src1
- v_cmp_ge_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u64 dst, src0, src1
- v_cmp_gt_f16 dst, src0, src1
- v_cmp_gt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f32 dst, src0, src1
- v_cmp_gt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f64 dst, src0, src1
- v_cmp_gt_i16 dst, src0, src1
- v_cmp_gt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i32 dst, src0, src1
- v_cmp_gt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i64 dst, src0, src1
- v_cmp_gt_u16 dst, src0, src1
- v_cmp_gt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u32 dst, src0, src1
- v_cmp_gt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u64 dst, src0, src1
- v_cmp_le_f16 dst, src0, src1
- v_cmp_le_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f32 dst, src0, src1
- v_cmp_le_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f64 dst, src0, src1
- v_cmp_le_i16 dst, src0, src1
- v_cmp_le_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i32 dst, src0, src1
- v_cmp_le_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i64 dst, src0, src1
- v_cmp_le_u16 dst, src0, src1
- v_cmp_le_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u32 dst, src0, src1
- v_cmp_le_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u64 dst, src0, src1
- v_cmp_lg_f16 dst, src0, src1
- v_cmp_lg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f32 dst, src0, src1
- v_cmp_lg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f64 dst, src0, src1
- v_cmp_lt_f16 dst, src0, src1
- v_cmp_lt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f32 dst, src0, src1
- v_cmp_lt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f64 dst, src0, src1
- v_cmp_lt_i16 dst, src0, src1
- v_cmp_lt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i32 dst, src0, src1
- v_cmp_lt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i64 dst, src0, src1
- v_cmp_lt_u16 dst, src0, src1
- v_cmp_lt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u32 dst, src0, src1
- v_cmp_lt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u64 dst, src0, src1
- v_cmp_ne_i16 dst, src0, src1
- v_cmp_ne_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i32 dst, src0, src1
- v_cmp_ne_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i64 dst, src0, src1
- v_cmp_ne_u16 dst, src0, src1
- v_cmp_ne_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u32 dst, src0, src1
- v_cmp_ne_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u64 dst, src0, src1
- v_cmp_neq_f16 dst, src0, src1
- v_cmp_neq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f32 dst, src0, src1
- v_cmp_neq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f64 dst, src0, src1
- v_cmp_nge_f16 dst, src0, src1
- v_cmp_nge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f32 dst, src0, src1
- v_cmp_nge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f64 dst, src0, src1
- v_cmp_ngt_f16 dst, src0, src1
- v_cmp_ngt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f32 dst, src0, src1
- v_cmp_ngt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f64 dst, src0, src1
- v_cmp_nle_f16 dst, src0, src1
- v_cmp_nle_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f32 dst, src0, src1
- v_cmp_nle_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f64 dst, src0, src1
- v_cmp_nlg_f16 dst, src0, src1
- v_cmp_nlg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f32 dst, src0, src1
- v_cmp_nlg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f64 dst, src0, src1
- v_cmp_nlt_f16 dst, src0, src1
- v_cmp_nlt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f32 dst, src0, src1
- v_cmp_nlt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f64 dst, src0, src1
- v_cmp_o_f16 dst, src0, src1
- v_cmp_o_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f32 dst, src0, src1
- v_cmp_o_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f64 dst, src0, src1
- v_cmp_t_i16 dst, src0, src1
- v_cmp_t_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_i32 dst, src0, src1
- v_cmp_t_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_i64 dst, src0, src1
- v_cmp_t_u16 dst, src0, src1
- v_cmp_t_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_u32 dst, src0, src1
- v_cmp_t_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_u64 dst, src0, src1
- v_cmp_tru_f16 dst, src0, src1
- v_cmp_tru_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f32 dst, src0, src1
- v_cmp_tru_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f64 dst, src0, src1
- v_cmp_u_f16 dst, src0, src1
- v_cmp_u_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f32 dst, src0, src1
- v_cmp_u_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f64 dst, src0, src1
- v_cmpx_class_f16 dst, src0, src1
- v_cmpx_class_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f32 dst, src0, src1
- v_cmpx_class_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f64 dst, src0, src1
- v_cmpx_eq_f16 dst, src0, src1
- v_cmpx_eq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f32 dst, src0, src1
- v_cmpx_eq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f64 dst, src0, src1
- v_cmpx_eq_i16 dst, src0, src1
- v_cmpx_eq_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i32 dst, src0, src1
- v_cmpx_eq_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i64 dst, src0, src1
- v_cmpx_eq_u16 dst, src0, src1
- v_cmpx_eq_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u32 dst, src0, src1
- v_cmpx_eq_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u64 dst, src0, src1
- v_cmpx_f_f16 dst, src0, src1
- v_cmpx_f_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f32 dst, src0, src1
- v_cmpx_f_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f64 dst, src0, src1
- v_cmpx_f_i16 dst, src0, src1
- v_cmpx_f_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_i32 dst, src0, src1
- v_cmpx_f_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_i64 dst, src0, src1
- v_cmpx_f_u16 dst, src0, src1
- v_cmpx_f_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_u32 dst, src0, src1
- v_cmpx_f_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_u64 dst, src0, src1
- v_cmpx_ge_f16 dst, src0, src1
- v_cmpx_ge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f32 dst, src0, src1
- v_cmpx_ge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f64 dst, src0, src1
- v_cmpx_ge_i16 dst, src0, src1
- v_cmpx_ge_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i32 dst, src0, src1
- v_cmpx_ge_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i64 dst, src0, src1
- v_cmpx_ge_u16 dst, src0, src1
- v_cmpx_ge_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u32 dst, src0, src1
- v_cmpx_ge_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u64 dst, src0, src1
- v_cmpx_gt_f16 dst, src0, src1
- v_cmpx_gt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f32 dst, src0, src1
- v_cmpx_gt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f64 dst, src0, src1
- v_cmpx_gt_i16 dst, src0, src1
- v_cmpx_gt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i32 dst, src0, src1
- v_cmpx_gt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i64 dst, src0, src1
- v_cmpx_gt_u16 dst, src0, src1
- v_cmpx_gt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u32 dst, src0, src1
- v_cmpx_gt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u64 dst, src0, src1
- v_cmpx_le_f16 dst, src0, src1
- v_cmpx_le_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f32 dst, src0, src1
- v_cmpx_le_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f64 dst, src0, src1
- v_cmpx_le_i16 dst, src0, src1
- v_cmpx_le_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i32 dst, src0, src1
- v_cmpx_le_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i64 dst, src0, src1
- v_cmpx_le_u16 dst, src0, src1
- v_cmpx_le_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u32 dst, src0, src1
- v_cmpx_le_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u64 dst, src0, src1
- v_cmpx_lg_f16 dst, src0, src1
- v_cmpx_lg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f32 dst, src0, src1
- v_cmpx_lg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f64 dst, src0, src1
- v_cmpx_lt_f16 dst, src0, src1
- v_cmpx_lt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f32 dst, src0, src1
- v_cmpx_lt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f64 dst, src0, src1
- v_cmpx_lt_i16 dst, src0, src1
- v_cmpx_lt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i32 dst, src0, src1
- v_cmpx_lt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i64 dst, src0, src1
- v_cmpx_lt_u16 dst, src0, src1
- v_cmpx_lt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u32 dst, src0, src1
- v_cmpx_lt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u64 dst, src0, src1
- v_cmpx_ne_i16 dst, src0, src1
- v_cmpx_ne_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i32 dst, src0, src1
- v_cmpx_ne_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i64 dst, src0, src1
- v_cmpx_ne_u16 dst, src0, src1
- v_cmpx_ne_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u32 dst, src0, src1
- v_cmpx_ne_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u64 dst, src0, src1
- v_cmpx_neq_f16 dst, src0, src1
- v_cmpx_neq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f32 dst, src0, src1
- v_cmpx_neq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f64 dst, src0, src1
- v_cmpx_nge_f16 dst, src0, src1
- v_cmpx_nge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f32 dst, src0, src1
- v_cmpx_nge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f64 dst, src0, src1
- v_cmpx_ngt_f16 dst, src0, src1
- v_cmpx_ngt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f32 dst, src0, src1
- v_cmpx_ngt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f64 dst, src0, src1
- v_cmpx_nle_f16 dst, src0, src1
- v_cmpx_nle_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f32 dst, src0, src1
- v_cmpx_nle_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f64 dst, src0, src1
- v_cmpx_nlg_f16 dst, src0, src1
- v_cmpx_nlg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f32 dst, src0, src1
- v_cmpx_nlg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f64 dst, src0, src1
- v_cmpx_nlt_f16 dst, src0, src1
- v_cmpx_nlt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f32 dst, src0, src1
- v_cmpx_nlt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f64 dst, src0, src1
- v_cmpx_o_f16 dst, src0, src1
- v_cmpx_o_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f32 dst, src0, src1
- v_cmpx_o_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f64 dst, src0, src1
- v_cmpx_t_i16 dst, src0, src1
- v_cmpx_t_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_i32 dst, src0, src1
- v_cmpx_t_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_i64 dst, src0, src1
- v_cmpx_t_u16 dst, src0, src1
- v_cmpx_t_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_u32 dst, src0, src1
- v_cmpx_t_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_u64 dst, src0, src1
- v_cmpx_tru_f16 dst, src0, src1
- v_cmpx_tru_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f32 dst, src0, src1
- v_cmpx_tru_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f64 dst, src0, src1
- v_cmpx_u_f16 dst, src0, src1
- v_cmpx_u_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f32 dst, src0, src1
- v_cmpx_u_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f64 dst, src0, src1
Removed: llvm/trunk/docs/AMDGPUAsmGFX9.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUAsmGFX9.rst?rev=349367&view=auto
==============================================================================
--- llvm/trunk/docs/AMDGPUAsmGFX9.rst (original)
+++ llvm/trunk/docs/AMDGPUAsmGFX9.rst (removed)
@@ -1,1906 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-===========================
-Syntax of GFX9 Instructions
-===========================
-
-.. contents::
- :local:
-
-
-DS
-===========================
-
-.. parsed-literal::
-
- ds_add_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_append dst :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_bpermute_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
- ds_cmpst_b32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_b64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_condxchg32_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_consume dst :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_barrier src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_init src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_br src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_p :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_release_all :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_v :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_nop
- ds_or_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_ordered_count dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_permute_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
- ds_read2_b32 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2_b64 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b32 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b64 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b128 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b32 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b64 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b96 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8_d16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8_d16_hi dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16_d16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16_d16_hi dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8_d16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8_d16_hi dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_swizzle_b32 dst, src0 :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrap_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b32 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b64 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b32 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b64 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b128 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b16 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b16_d16_hi src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b8 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b8_d16_hi src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b96 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
-
-EXP
-===========================
-
-.. parsed-literal::
-
- exp dst, src0, src1, src2, src3 :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
-
-FLAT
-===========================
-
-.. parsed-literal::
-
- flat_atomic_add dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_add_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor_x2 dst, src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dword dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx2 dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx3 dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx4 dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sbyte dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sbyte_d16 dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sbyte_d16_hi dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_short_d16 dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_short_d16_hi dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sshort dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ubyte dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ubyte_d16 dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ubyte_d16_hi dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ushort dst, src0 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_byte src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_byte_d16_hi src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dword src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx2 src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx3 src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx4 src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_short src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_short_d16_hi src0, src1 :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_add dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_add_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_and dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_and_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_cmpswap dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_cmpswap_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_dec dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_dec_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_inc dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_inc_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_or dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_or_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_smax dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_smax_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_smin dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_smin_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_sub dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_sub_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_swap dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_swap_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_umax dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_umax_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_umin dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_umin_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_xor dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_atomic_xor_x2 dst, src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_dword dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_dwordx2 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_dwordx3 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_dwordx4 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_sbyte dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_sbyte_d16 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_sbyte_d16_hi dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_short_d16 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_short_d16_hi dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_sshort dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_ubyte dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_ubyte_d16 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_ubyte_d16_hi dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_load_ushort dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_byte src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_byte_d16_hi src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_dword src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_dwordx2 src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_dwordx3 src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_dwordx4 src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_short src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- global_store_short_d16_hi src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
- scratch_load_dword dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_dwordx2 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_dwordx3 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_dwordx4 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sbyte dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sbyte_d16 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sbyte_d16_hi dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_short_d16 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_short_d16_hi dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sshort dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ubyte dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ubyte_d16 dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ubyte_d16_hi dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ushort dst, src0, src1 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_byte src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_byte_d16_hi src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dword src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dwordx2 src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dwordx3 src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dwordx4 src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_short src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_short_d16_hi src0, src1, src2 :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-
-MIMG
-===========================
-
-.. parsed-literal::
-
- image_atomic_add dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_and dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_cmpswap dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_dec dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_inc dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_or dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smax dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smin dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_sub dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_swap dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umax dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umin dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_xor dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4 dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_get_lod dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_get_resinfo dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip_pck dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_mip_pck_sgn dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck_sgn dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_lz_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip_pck src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_store_pck src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-
-MUBUF
-===========================
-
-.. parsed-literal::
-
- buffer_atomic_add dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_add_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dword dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_dwordx2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx3 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx4 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_hi_x dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_x dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xy dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xyz dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xyzw dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_x dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_format_xy dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyz dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyzw dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sbyte dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_sbyte_d16 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sbyte_d16_hi dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_short_d16 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_short_d16_hi dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sshort dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte_d16 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_ubyte_d16_hi dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_ushort dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_byte src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_byte_d16_hi src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dword src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx2 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx3 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx4 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_hi_x src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_x src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xy src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyz src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyzw src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_x src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xy src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyz src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyzw src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_lds_dword src0, src1 :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_short src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short_d16_hi src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_wbinvl1
- buffer_wbinvl1_vol
-
-SMEM
-===========================
-
-.. parsed-literal::
-
- s_atc_probe src0, src1, src2
- s_atc_probe_buffer src0, src1, src2
- s_atomic_add dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_add_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dword dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx16 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx4 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx8 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dword src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx2 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx4 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_dcache_discard src0, src1
- s_dcache_discard_x2 src0, src1
- s_dcache_inv
- s_dcache_inv_vol
- s_dcache_wb
- s_dcache_wb_vol
- s_load_dword dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx16 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx4 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx8 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_memrealtime dst
- s_memtime dst
- s_scratch_load_dword dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_scratch_load_dwordx2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_scratch_load_dwordx4 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dword src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx2 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx4 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_store_dword src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx2 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx4 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>`
-
-SOP1
-===========================
-
-.. parsed-literal::
-
- s_abs_i32 dst, src0
- s_and_saveexec_b64 dst, src0
- s_andn1_saveexec_b64 dst, src0
- s_andn1_wrexec_b64 dst, src0
- s_andn2_saveexec_b64 dst, src0
- s_andn2_wrexec_b64 dst, src0
- s_bcnt0_i32_b32 dst, src0
- s_bcnt0_i32_b64 dst, src0
- s_bcnt1_i32_b32 dst, src0
- s_bcnt1_i32_b64 dst, src0
- s_bitreplicate_b64_b32 dst, src0
- s_bitset0_b32 dst, src0
- s_bitset0_b64 dst, src0
- s_bitset1_b32 dst, src0
- s_bitset1_b64 dst, src0
- s_brev_b32 dst, src0
- s_brev_b64 dst, src0
- s_cbranch_join src0
- s_cmov_b32 dst, src0
- s_cmov_b64 dst, src0
- s_ff0_i32_b32 dst, src0
- s_ff0_i32_b64 dst, src0
- s_ff1_i32_b32 dst, src0
- s_ff1_i32_b64 dst, src0
- s_flbit_i32 dst, src0
- s_flbit_i32_b32 dst, src0
- s_flbit_i32_b64 dst, src0
- s_flbit_i32_i64 dst, src0
- s_getpc_b64 dst
- s_mov_b32 dst, src0
- s_mov_b64 dst, src0
- s_mov_fed_b32 dst, src0
- s_movreld_b32 dst, src0
- s_movreld_b64 dst, src0
- s_movrels_b32 dst, src0
- s_movrels_b64 dst, src0
- s_nand_saveexec_b64 dst, src0
- s_nor_saveexec_b64 dst, src0
- s_not_b32 dst, src0
- s_not_b64 dst, src0
- s_or_saveexec_b64 dst, src0
- s_orn1_saveexec_b64 dst, src0
- s_orn2_saveexec_b64 dst, src0
- s_quadmask_b32 dst, src0
- s_quadmask_b64 dst, src0
- s_rfe_b64 src0
- s_set_gpr_idx_idx src0
- s_setpc_b64 src0
- s_sext_i32_i16 dst, src0
- s_sext_i32_i8 dst, src0
- s_swappc_b64 dst, src0
- s_wqm_b32 dst, src0
- s_wqm_b64 dst, src0
- s_xnor_saveexec_b64 dst, src0
- s_xor_saveexec_b64 dst, src0
-
-SOP2
-===========================
-
-.. parsed-literal::
-
- s_absdiff_i32 dst, src0, src1
- s_add_i32 dst, src0, src1
- s_add_u32 dst, src0, src1
- s_addc_u32 dst, src0, src1
- s_and_b32 dst, src0, src1
- s_and_b64 dst, src0, src1
- s_andn2_b32 dst, src0, src1
- s_andn2_b64 dst, src0, src1
- s_ashr_i32 dst, src0, src1
- s_ashr_i64 dst, src0, src1
- s_bfe_i32 dst, src0, src1
- s_bfe_i64 dst, src0, src1
- s_bfe_u32 dst, src0, src1
- s_bfe_u64 dst, src0, src1
- s_bfm_b32 dst, src0, src1
- s_bfm_b64 dst, src0, src1
- s_cbranch_g_fork src0, src1
- s_cselect_b32 dst, src0, src1
- s_cselect_b64 dst, src0, src1
- s_lshl1_add_u32 dst, src0, src1
- s_lshl2_add_u32 dst, src0, src1
- s_lshl3_add_u32 dst, src0, src1
- s_lshl4_add_u32 dst, src0, src1
- s_lshl_b32 dst, src0, src1
- s_lshl_b64 dst, src0, src1
- s_lshr_b32 dst, src0, src1
- s_lshr_b64 dst, src0, src1
- s_max_i32 dst, src0, src1
- s_max_u32 dst, src0, src1
- s_min_i32 dst, src0, src1
- s_min_u32 dst, src0, src1
- s_mul_hi_i32 dst, src0, src1
- s_mul_hi_u32 dst, src0, src1
- s_mul_i32 dst, src0, src1
- s_nand_b32 dst, src0, src1
- s_nand_b64 dst, src0, src1
- s_nor_b32 dst, src0, src1
- s_nor_b64 dst, src0, src1
- s_or_b32 dst, src0, src1
- s_or_b64 dst, src0, src1
- s_orn2_b32 dst, src0, src1
- s_orn2_b64 dst, src0, src1
- s_pack_hh_b32_b16 dst, src0, src1
- s_pack_lh_b32_b16 dst, src0, src1
- s_pack_ll_b32_b16 dst, src0, src1
- s_rfe_restore_b64 src0, src1
- s_sub_i32 dst, src0, src1
- s_sub_u32 dst, src0, src1
- s_subb_u32 dst, src0, src1
- s_xnor_b32 dst, src0, src1
- s_xnor_b64 dst, src0, src1
- s_xor_b32 dst, src0, src1
- s_xor_b64 dst, src0, src1
-
-SOPC
-===========================
-
-.. parsed-literal::
-
- s_bitcmp0_b32 src0, src1
- s_bitcmp0_b64 src0, src1
- s_bitcmp1_b32 src0, src1
- s_bitcmp1_b64 src0, src1
- s_cmp_eq_i32 src0, src1
- s_cmp_eq_u32 src0, src1
- s_cmp_eq_u64 src0, src1
- s_cmp_ge_i32 src0, src1
- s_cmp_ge_u32 src0, src1
- s_cmp_gt_i32 src0, src1
- s_cmp_gt_u32 src0, src1
- s_cmp_le_i32 src0, src1
- s_cmp_le_u32 src0, src1
- s_cmp_lg_i32 src0, src1
- s_cmp_lg_u32 src0, src1
- s_cmp_lg_u64 src0, src1
- s_cmp_lt_i32 src0, src1
- s_cmp_lt_u32 src0, src1
- s_set_gpr_idx_on src0, src1
- s_setvskip src0, src1
-
-SOPK
-===========================
-
-.. parsed-literal::
-
- s_addk_i32 dst, src0
- s_call_b64 dst, src0
- s_cbranch_i_fork src0, src1
- s_cmovk_i32 dst, src0
- s_cmpk_eq_i32 src0, src1
- s_cmpk_eq_u32 src0, src1
- s_cmpk_ge_i32 src0, src1
- s_cmpk_ge_u32 src0, src1
- s_cmpk_gt_i32 src0, src1
- s_cmpk_gt_u32 src0, src1
- s_cmpk_le_i32 src0, src1
- s_cmpk_le_u32 src0, src1
- s_cmpk_lg_i32 src0, src1
- s_cmpk_lg_u32 src0, src1
- s_cmpk_lt_i32 src0, src1
- s_cmpk_lt_u32 src0, src1
- s_getreg_b32 dst, src0
- s_movk_i32 dst, src0
- s_mulk_i32 dst, src0
- s_setreg_b32 dst, src0
- s_setreg_imm32_b32 dst, src0
-
-SOPP
-===========================
-
-.. parsed-literal::
-
- s_barrier
- s_branch src0
- s_cbranch_cdbgsys src0
- s_cbranch_cdbgsys_and_user src0
- s_cbranch_cdbgsys_or_user src0
- s_cbranch_cdbguser src0
- s_cbranch_execnz src0
- s_cbranch_execz src0
- s_cbranch_scc0 src0
- s_cbranch_scc1 src0
- s_cbranch_vccnz src0
- s_cbranch_vccz src0
- s_decperflevel src0
- s_endpgm
- s_endpgm_ordered_ps_done
- s_endpgm_saved
- s_icache_inv
- s_incperflevel src0
- s_nop src0
- s_sendmsg src0
- s_sendmsghalt src0
- s_set_gpr_idx_mode src0
- s_set_gpr_idx_off
- s_sethalt src0
- s_setkill src0
- s_setprio src0
- s_sleep src0
- s_trap src0
- s_ttracedata
- s_waitcnt src0
- s_wakeup
-
-VINTRP
-===========================
-
-.. parsed-literal::
-
- v_interp_mov_f32 dst, src0, src1
- v_interp_p1_f32 dst, src0, src1
- v_interp_p2_f32 dst, src0, src1
-
-VOP1
-===========================
-
-.. parsed-literal::
-
- v_bfrev_b32 dst, src0
- v_bfrev_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_bfrev_b32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f16 dst, src0
- v_ceil_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ceil_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f32 dst, src0
- v_ceil_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ceil_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f64 dst, src0
- v_clrexcp
- v_cos_f16 dst, src0
- v_cos_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cos_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cos_f32 dst, src0
- v_cos_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cos_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_f32 dst, src0
- v_cvt_f16_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_i16 dst, src0
- v_cvt_f16_i16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_i16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_u16 dst, src0
- v_cvt_f16_u16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_u16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_f16 dst, src0
- v_cvt_f32_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_f64 dst, src0
- v_cvt_f32_i32 dst, src0
- v_cvt_f32_i32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_i32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_u32 dst, src0
- v_cvt_f32_u32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_u32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte0 dst, src0
- v_cvt_f32_ubyte0_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte0_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte1 dst, src0
- v_cvt_f32_ubyte1_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte1_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte2 dst, src0
- v_cvt_f32_ubyte2_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte2_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte3 dst, src0
- v_cvt_f32_ubyte3_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte3_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f64_f32 dst, src0
- v_cvt_f64_i32 dst, src0
- v_cvt_f64_u32 dst, src0
- v_cvt_flr_i32_f32 dst, src0
- v_cvt_flr_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_flr_i32_f32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i16_f16 dst, src0
- v_cvt_i16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_i16_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i32_f32 dst, src0
- v_cvt_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_i32_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i32_f64 dst, src0
- v_cvt_norm_i16_f16 dst, src0
- v_cvt_norm_i16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_norm_i16_f16_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_norm_u16_f16 dst, src0
- v_cvt_norm_u16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_norm_u16_f16_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_off_f32_i4 dst, src0
- v_cvt_off_f32_i4_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_off_f32_i4_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_rpi_i32_f32 dst, src0
- v_cvt_rpi_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_rpi_i32_f32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u16_f16 dst, src0
- v_cvt_u16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_u16_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u32_f32 dst, src0
- v_cvt_u32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_u32_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u32_f64 dst, src0
- v_exp_f16 dst, src0
- v_exp_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_f32 dst, src0
- v_exp_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_legacy_f32 dst, src0
- v_exp_legacy_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_legacy_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_i32 dst, src0
- v_ffbh_i32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbh_i32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_u32 dst, src0
- v_ffbh_u32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbh_u32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbl_b32 dst, src0
- v_ffbl_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbl_b32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f16 dst, src0
- v_floor_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_floor_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f32 dst, src0
- v_floor_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_floor_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f64 dst, src0
- v_fract_f16 dst, src0
- v_fract_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_fract_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f32 dst, src0
- v_fract_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_fract_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f64 dst, src0
- v_frexp_exp_i16_f16 dst, src0
- v_frexp_exp_i16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_exp_i16_f16_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i32_f32 dst, src0
- v_frexp_exp_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_exp_i32_f32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i32_f64 dst, src0
- v_frexp_mant_f16 dst, src0
- v_frexp_mant_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_mant_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f32 dst, src0
- v_frexp_mant_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_mant_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f64 dst, src0
- v_log_f16 dst, src0
- v_log_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_log_f32 dst, src0
- v_log_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_log_legacy_f32 dst, src0
- v_log_legacy_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_legacy_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_mov_b32 dst, src0
- v_mov_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mov_b32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_mov_fed_b32 dst, src0
- v_mov_fed_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mov_fed_b32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_nop
- v_not_b32 dst, src0
- v_not_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_not_b32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f16 dst, src0
- v_rcp_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f32 dst, src0
- v_rcp_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f64 dst, src0
- v_rcp_iflag_f32 dst, src0
- v_rcp_iflag_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_iflag_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_readfirstlane_b32 dst, src0
- v_rndne_f16 dst, src0
- v_rndne_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rndne_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f32 dst, src0
- v_rndne_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rndne_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f64 dst, src0
- v_rsq_f16 dst, src0
- v_rsq_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rsq_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f32 dst, src0
- v_rsq_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rsq_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f64 dst, src0
- v_sat_pk_u8_i16 dst, src0
- v_sat_pk_u8_i16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sat_pk_u8_i16_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_screen_partition_4se_b32 dst, src0
- v_screen_partition_4se_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_screen_partition_4se_b32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sin_f16 dst, src0
- v_sin_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sin_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sin_f32 dst, src0
- v_sin_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sin_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f16 dst, src0
- v_sqrt_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sqrt_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f32 dst, src0
- v_sqrt_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sqrt_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f64 dst, src0
- v_swap_b32 dst, src0
- v_trunc_f16 dst, src0
- v_trunc_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_trunc_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_trunc_f32 dst, src0
- v_trunc_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_trunc_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_trunc_f64 dst, src0
-
-VOP2
-===========================
-
-.. parsed-literal::
-
- v_add_co_u32 dst0, dst1, src0, src1
- v_add_co_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_co_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_f16 dst, src0, src1
- v_add_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_f32 dst, src0, src1
- v_add_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_u16 dst, src0, src1
- v_add_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_u32 dst, src0, src1
- v_add_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_u32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_addc_co_u32 dst0, dst1, src0, src1, src2
- v_addc_co_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_addc_co_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_and_b32 dst, src0, src1
- v_and_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_and_b32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i16 dst, src0, src1
- v_ashrrev_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i32 dst, src0, src1
- v_ashrrev_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cndmask_b32 dst, src0, src1, src2
- v_cndmask_b32_dpp dst, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cndmask_b32_sdwa dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ldexp_f16 dst, src0, src1
- v_ldexp_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ldexp_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b16 dst, src0, src1
- v_lshlrev_b16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b32 dst, src0, src1
- v_lshlrev_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b16 dst, src0, src1
- v_lshrrev_b16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b32 dst, src0, src1
- v_lshrrev_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mac_f16 dst, src0, src1
- v_mac_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mac_f32 dst, src0, src1
- v_mac_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_madak_f16 dst, src0, src1, src2
- v_madak_f32 dst, src0, src1, src2
- v_madmk_f16 dst, src0, src1, src2
- v_madmk_f32 dst, src0, src1, src2
- v_max_f16 dst, src0, src1
- v_max_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_f32 dst, src0, src1
- v_max_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_i16 dst, src0, src1
- v_max_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_i16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_i32 dst, src0, src1
- v_max_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_i32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_u16 dst, src0, src1
- v_max_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_u16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_u32 dst, src0, src1
- v_max_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_u32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f16 dst, src0, src1
- v_min_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f32 dst, src0, src1
- v_min_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_i16 dst, src0, src1
- v_min_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_i16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_i32 dst, src0, src1
- v_min_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_i32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_u16 dst, src0, src1
- v_min_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_u16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_u32 dst, src0, src1
- v_min_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_u32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_f16 dst, src0, src1
- v_mul_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_f32 dst, src0, src1
- v_mul_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_i32_i24 dst, src0, src1
- v_mul_hi_i32_i24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_hi_i32_i24_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_u32_u24 dst, src0, src1
- v_mul_hi_u32_u24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_hi_u32_u24_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_i32_i24 dst, src0, src1
- v_mul_i32_i24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_i32_i24_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_legacy_f32 dst, src0, src1
- v_mul_legacy_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_legacy_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_lo_u16 dst, src0, src1
- v_mul_lo_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_lo_u16_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_u32_u24 dst, src0, src1
- v_mul_u32_u24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_u32_u24_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_or_b32 dst, src0, src1
- v_or_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_or_b32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_co_u32 dst0, dst1, src0, src1
- v_sub_co_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_co_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f16 dst, src0, src1
- v_sub_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f32 dst, src0, src1
- v_sub_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_u16 dst, src0, src1
- v_sub_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_u32 dst, src0, src1
- v_sub_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_u32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subb_co_u32 dst0, dst1, src0, src1, src2
- v_subb_co_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subb_co_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subbrev_co_u32 dst0, dst1, src0, src1, src2
- v_subbrev_co_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subbrev_co_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_co_u32 dst0, dst1, src0, src1
- v_subrev_co_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_co_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f16 dst, src0, src1
- v_subrev_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f32 dst, src0, src1
- v_subrev_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u16 dst, src0, src1
- v_subrev_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u32 dst, src0, src1
- v_subrev_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_xor_b32 dst, src0, src1
- v_xor_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_xor_b32_sdwa dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-
-VOP3
-===========================
-
-.. parsed-literal::
-
- v_add3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_add_co_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_add_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_i16 dst, src0, src1 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_add_lshl_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_add_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_add_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_addc_co_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_alignbit_b32 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_alignbyte_b32 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_and_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_and_or_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_ashrrev_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_ashrrev_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_ashrrev_i64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_bcnt_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_bfe_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_bfe_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_bfi_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_bfm_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_bfrev_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_clrexcp_e64 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_class_f16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_class_f32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_class_f64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_eq_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_f_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ge_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_gt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_le_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_lt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ne_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_neq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_neq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_neq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ngt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ngt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_ngt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nle_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nle_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nle_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_nlt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_o_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_o_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_o_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_t_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmp_tru_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_tru_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_tru_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_u_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_u_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmp_u_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_class_f16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_class_f32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_class_f64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_eq_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_f_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ge_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_gt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_le_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_lt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ne_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_neq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_neq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_neq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ngt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ngt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_ngt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nle_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nle_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nle_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_nlt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_o_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_o_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_o_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_t_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_tru_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_tru_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_tru_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_u_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_u_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cmpx_u_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cndmask_b32_e64 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_cos_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cos_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubeid_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubema_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubesc_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubetc_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_i16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_u16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_i32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_u32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte0_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte1_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte2_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte3_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_i32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_u32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_flr_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_i16_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_i32_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_i32_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_norm_i16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_norm_u16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_off_f32_i4_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_i16_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_u16_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_u8_f32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pkaccum_u8_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pknorm_i16_f16 dst, src0, src1 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pknorm_i16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pknorm_u16_f16 dst, src0, src1 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pknorm_u16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pkrtz_f16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_rpi_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_cvt_u16_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_u32_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_u32_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_legacy_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f32 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_exp_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_legacy_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_i32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_u32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_ffbl_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_floor_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_floor_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_floor_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_legacy_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i32_f64_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_mov_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1ll_f16 dst, src0, src1 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1lv_f16 dst, src0, src1, src2 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_legacy_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f32 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lerp_u8 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_log_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_legacy_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lshl_add_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_lshl_or_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_lshlrev_b16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshlrev_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshlrev_b64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshrrev_b16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshrrev_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_lshrrev_b64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mac_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mac_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i32_i16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i32_i24 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i64_i32 dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_legacy_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_legacy_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_legacy_i16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_legacy_u16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u32_u16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u32_u24 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u64_u32 dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_max3_u16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_max_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_max_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_max_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_max_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mbcnt_hi_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mbcnt_lo_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_med3_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_med3_u16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_min3_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_min3_u16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_min_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_min_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_min_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_min_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mov_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_mov_fed_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_mqsad_pk_u16_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mqsad_u32_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_msad_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32_i24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_u32_u24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_i32_i24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_legacy_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_mul_u32_u24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_nop_e64 :ref:`omod<amdgpu_synid_omod>`
- v_not_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_or3_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_or_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_pack_b32_f16 dst, src0, src1 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
- v_perm_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_qsad_pk_u16_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_iflag_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_readlane_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_hi_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_u16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_u32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sat_pk_u8_i16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_screen_partition_4se_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>`
- v_sin_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sin_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_co_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_sub_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_i16 dst, src0, src1 :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_sub_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_sub_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_subb_co_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_subbrev_co_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_subrev_co_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_subrev_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_subrev_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_trig_preop_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_writelane_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
- v_xad_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
- v_xor_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
-
-VOP3P
-===========================
-
-.. parsed-literal::
-
- v_mad_mix_f32 dst, src0, src1, src2 :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_mixhi_f16 dst, src0, src1, src2 :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_mixlo_f16 dst, src0, src1, src2 :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_f16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_i16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_u16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_ashrrev_i16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_fma_f16 dst, src0, src1, src2 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_lshlrev_b16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_lshrrev_b16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mad_i16 dst, src0, src1, src2 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mad_u16 dst, src0, src1, src2 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_f16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_i16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_max_u16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_f16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_min_i16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_u16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mul_f16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mul_lo_u16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_sub_i16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_sub_u16 dst, src0, src1 :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-
-VOPC
-===========================
-
-.. parsed-literal::
-
- v_cmp_class_f16 dst, src0, src1
- v_cmp_class_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_class_f32 dst, src0, src1
- v_cmp_class_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_class_f64 dst, src0, src1
- v_cmp_eq_f16 dst, src0, src1
- v_cmp_eq_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f32 dst, src0, src1
- v_cmp_eq_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f64 dst, src0, src1
- v_cmp_eq_i16 dst, src0, src1
- v_cmp_eq_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i32 dst, src0, src1
- v_cmp_eq_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i64 dst, src0, src1
- v_cmp_eq_u16 dst, src0, src1
- v_cmp_eq_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u32 dst, src0, src1
- v_cmp_eq_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u64 dst, src0, src1
- v_cmp_f_f16 dst, src0, src1
- v_cmp_f_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f32 dst, src0, src1
- v_cmp_f_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f64 dst, src0, src1
- v_cmp_f_i16 dst, src0, src1
- v_cmp_f_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_i32 dst, src0, src1
- v_cmp_f_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_i64 dst, src0, src1
- v_cmp_f_u16 dst, src0, src1
- v_cmp_f_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_u32 dst, src0, src1
- v_cmp_f_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_u64 dst, src0, src1
- v_cmp_ge_f16 dst, src0, src1
- v_cmp_ge_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f32 dst, src0, src1
- v_cmp_ge_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f64 dst, src0, src1
- v_cmp_ge_i16 dst, src0, src1
- v_cmp_ge_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i32 dst, src0, src1
- v_cmp_ge_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i64 dst, src0, src1
- v_cmp_ge_u16 dst, src0, src1
- v_cmp_ge_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u32 dst, src0, src1
- v_cmp_ge_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u64 dst, src0, src1
- v_cmp_gt_f16 dst, src0, src1
- v_cmp_gt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f32 dst, src0, src1
- v_cmp_gt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f64 dst, src0, src1
- v_cmp_gt_i16 dst, src0, src1
- v_cmp_gt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i32 dst, src0, src1
- v_cmp_gt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i64 dst, src0, src1
- v_cmp_gt_u16 dst, src0, src1
- v_cmp_gt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u32 dst, src0, src1
- v_cmp_gt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u64 dst, src0, src1
- v_cmp_le_f16 dst, src0, src1
- v_cmp_le_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f32 dst, src0, src1
- v_cmp_le_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f64 dst, src0, src1
- v_cmp_le_i16 dst, src0, src1
- v_cmp_le_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i32 dst, src0, src1
- v_cmp_le_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i64 dst, src0, src1
- v_cmp_le_u16 dst, src0, src1
- v_cmp_le_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u32 dst, src0, src1
- v_cmp_le_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u64 dst, src0, src1
- v_cmp_lg_f16 dst, src0, src1
- v_cmp_lg_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f32 dst, src0, src1
- v_cmp_lg_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f64 dst, src0, src1
- v_cmp_lt_f16 dst, src0, src1
- v_cmp_lt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f32 dst, src0, src1
- v_cmp_lt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f64 dst, src0, src1
- v_cmp_lt_i16 dst, src0, src1
- v_cmp_lt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i32 dst, src0, src1
- v_cmp_lt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i64 dst, src0, src1
- v_cmp_lt_u16 dst, src0, src1
- v_cmp_lt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u32 dst, src0, src1
- v_cmp_lt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u64 dst, src0, src1
- v_cmp_ne_i16 dst, src0, src1
- v_cmp_ne_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i32 dst, src0, src1
- v_cmp_ne_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i64 dst, src0, src1
- v_cmp_ne_u16 dst, src0, src1
- v_cmp_ne_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u32 dst, src0, src1
- v_cmp_ne_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u64 dst, src0, src1
- v_cmp_neq_f16 dst, src0, src1
- v_cmp_neq_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f32 dst, src0, src1
- v_cmp_neq_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f64 dst, src0, src1
- v_cmp_nge_f16 dst, src0, src1
- v_cmp_nge_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f32 dst, src0, src1
- v_cmp_nge_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f64 dst, src0, src1
- v_cmp_ngt_f16 dst, src0, src1
- v_cmp_ngt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f32 dst, src0, src1
- v_cmp_ngt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f64 dst, src0, src1
- v_cmp_nle_f16 dst, src0, src1
- v_cmp_nle_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f32 dst, src0, src1
- v_cmp_nle_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f64 dst, src0, src1
- v_cmp_nlg_f16 dst, src0, src1
- v_cmp_nlg_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f32 dst, src0, src1
- v_cmp_nlg_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f64 dst, src0, src1
- v_cmp_nlt_f16 dst, src0, src1
- v_cmp_nlt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f32 dst, src0, src1
- v_cmp_nlt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f64 dst, src0, src1
- v_cmp_o_f16 dst, src0, src1
- v_cmp_o_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f32 dst, src0, src1
- v_cmp_o_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f64 dst, src0, src1
- v_cmp_t_i16 dst, src0, src1
- v_cmp_t_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_i32 dst, src0, src1
- v_cmp_t_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_i64 dst, src0, src1
- v_cmp_t_u16 dst, src0, src1
- v_cmp_t_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_u32 dst, src0, src1
- v_cmp_t_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_u64 dst, src0, src1
- v_cmp_tru_f16 dst, src0, src1
- v_cmp_tru_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f32 dst, src0, src1
- v_cmp_tru_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f64 dst, src0, src1
- v_cmp_u_f16 dst, src0, src1
- v_cmp_u_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f32 dst, src0, src1
- v_cmp_u_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f64 dst, src0, src1
- v_cmpx_class_f16 dst, src0, src1
- v_cmpx_class_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f32 dst, src0, src1
- v_cmpx_class_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f64 dst, src0, src1
- v_cmpx_eq_f16 dst, src0, src1
- v_cmpx_eq_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f32 dst, src0, src1
- v_cmpx_eq_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f64 dst, src0, src1
- v_cmpx_eq_i16 dst, src0, src1
- v_cmpx_eq_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i32 dst, src0, src1
- v_cmpx_eq_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i64 dst, src0, src1
- v_cmpx_eq_u16 dst, src0, src1
- v_cmpx_eq_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u32 dst, src0, src1
- v_cmpx_eq_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u64 dst, src0, src1
- v_cmpx_f_f16 dst, src0, src1
- v_cmpx_f_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f32 dst, src0, src1
- v_cmpx_f_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f64 dst, src0, src1
- v_cmpx_f_i16 dst, src0, src1
- v_cmpx_f_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_i32 dst, src0, src1
- v_cmpx_f_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_i64 dst, src0, src1
- v_cmpx_f_u16 dst, src0, src1
- v_cmpx_f_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_u32 dst, src0, src1
- v_cmpx_f_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_u64 dst, src0, src1
- v_cmpx_ge_f16 dst, src0, src1
- v_cmpx_ge_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f32 dst, src0, src1
- v_cmpx_ge_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f64 dst, src0, src1
- v_cmpx_ge_i16 dst, src0, src1
- v_cmpx_ge_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i32 dst, src0, src1
- v_cmpx_ge_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i64 dst, src0, src1
- v_cmpx_ge_u16 dst, src0, src1
- v_cmpx_ge_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u32 dst, src0, src1
- v_cmpx_ge_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u64 dst, src0, src1
- v_cmpx_gt_f16 dst, src0, src1
- v_cmpx_gt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f32 dst, src0, src1
- v_cmpx_gt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f64 dst, src0, src1
- v_cmpx_gt_i16 dst, src0, src1
- v_cmpx_gt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i32 dst, src0, src1
- v_cmpx_gt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i64 dst, src0, src1
- v_cmpx_gt_u16 dst, src0, src1
- v_cmpx_gt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u32 dst, src0, src1
- v_cmpx_gt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u64 dst, src0, src1
- v_cmpx_le_f16 dst, src0, src1
- v_cmpx_le_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f32 dst, src0, src1
- v_cmpx_le_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f64 dst, src0, src1
- v_cmpx_le_i16 dst, src0, src1
- v_cmpx_le_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i32 dst, src0, src1
- v_cmpx_le_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i64 dst, src0, src1
- v_cmpx_le_u16 dst, src0, src1
- v_cmpx_le_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u32 dst, src0, src1
- v_cmpx_le_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u64 dst, src0, src1
- v_cmpx_lg_f16 dst, src0, src1
- v_cmpx_lg_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f32 dst, src0, src1
- v_cmpx_lg_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f64 dst, src0, src1
- v_cmpx_lt_f16 dst, src0, src1
- v_cmpx_lt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f32 dst, src0, src1
- v_cmpx_lt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f64 dst, src0, src1
- v_cmpx_lt_i16 dst, src0, src1
- v_cmpx_lt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i32 dst, src0, src1
- v_cmpx_lt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i64 dst, src0, src1
- v_cmpx_lt_u16 dst, src0, src1
- v_cmpx_lt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u32 dst, src0, src1
- v_cmpx_lt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u64 dst, src0, src1
- v_cmpx_ne_i16 dst, src0, src1
- v_cmpx_ne_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i32 dst, src0, src1
- v_cmpx_ne_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i64 dst, src0, src1
- v_cmpx_ne_u16 dst, src0, src1
- v_cmpx_ne_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u32 dst, src0, src1
- v_cmpx_ne_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u64 dst, src0, src1
- v_cmpx_neq_f16 dst, src0, src1
- v_cmpx_neq_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f32 dst, src0, src1
- v_cmpx_neq_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f64 dst, src0, src1
- v_cmpx_nge_f16 dst, src0, src1
- v_cmpx_nge_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f32 dst, src0, src1
- v_cmpx_nge_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f64 dst, src0, src1
- v_cmpx_ngt_f16 dst, src0, src1
- v_cmpx_ngt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f32 dst, src0, src1
- v_cmpx_ngt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f64 dst, src0, src1
- v_cmpx_nle_f16 dst, src0, src1
- v_cmpx_nle_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f32 dst, src0, src1
- v_cmpx_nle_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f64 dst, src0, src1
- v_cmpx_nlg_f16 dst, src0, src1
- v_cmpx_nlg_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f32 dst, src0, src1
- v_cmpx_nlg_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f64 dst, src0, src1
- v_cmpx_nlt_f16 dst, src0, src1
- v_cmpx_nlt_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f32 dst, src0, src1
- v_cmpx_nlt_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f64 dst, src0, src1
- v_cmpx_o_f16 dst, src0, src1
- v_cmpx_o_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f32 dst, src0, src1
- v_cmpx_o_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f64 dst, src0, src1
- v_cmpx_t_i16 dst, src0, src1
- v_cmpx_t_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_i32 dst, src0, src1
- v_cmpx_t_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_i64 dst, src0, src1
- v_cmpx_t_u16 dst, src0, src1
- v_cmpx_t_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_u32 dst, src0, src1
- v_cmpx_t_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_u64 dst, src0, src1
- v_cmpx_tru_f16 dst, src0, src1
- v_cmpx_tru_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f32 dst, src0, src1
- v_cmpx_tru_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f64 dst, src0, src1
- v_cmpx_u_f16 dst, src0, src1
- v_cmpx_u_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f32 dst, src0, src1
- v_cmpx_u_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f64 dst, src0, src1
Added: llvm/trunk/docs/AMDGPUInstructionNotation.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUInstructionNotation.rst?rev=349368&view=auto
==============================================================================
--- llvm/trunk/docs/AMDGPUInstructionNotation.rst (added)
+++ llvm/trunk/docs/AMDGPUInstructionNotation.rst Mon Dec 17 09:38:11 2018
@@ -0,0 +1,110 @@
+============================
+AMDGPU Instructions Notation
+============================
+
+.. contents::
+ :local:
+
+.. _amdgpu_syn_instruction_notation:
+
+Introduction
+============
+
+This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.
+
+This notation mimics the :ref:`syntax of assembler instructions<amdgpu_syn_instructions>`
+except that instead of real operands and modifiers it provides references to their description.
+
+Instructions
+============
+
+Notation
+~~~~~~~~
+
+This is the notation used to describe AMDGPU instructions:
+
+ ``<``\ :ref:`opcode description<amdgpu_syn_opcode_notation>`\ ``> <``\ :ref:`operands description<amdgpu_syn_instruction_operands_notation>`\ ``> <``\ :ref:`modifiers description<amdgpu_syn_instruction_modifiers_notation>`\ ``>``
+
+.. _amdgpu_syn_opcode_notation:
+
+Opcode
+======
+
+Notation
+~~~~~~~~
+
+TBD
+
+.. _amdgpu_syn_instruction_operands_notation:
+
+Operands
+========
+
+An instruction may have zero or more *operands*. They are comma-separated in the description:
+
+ ``<``\ :ref:`description of operand 0<amdgpu_syn_instruction_operand_notation>`\ ``>, <``\ :ref:`description of operand 1<amdgpu_syn_instruction_operand_notation>`\ ``>, ...``
+
+The order of *operands* is fixed. *Operands* cannot be omitted
+except for special cases described below.
+
+.. _amdgpu_syn_instruction_operand_notation:
+
+Notation
+~~~~~~~~
+
+An operand is described using the following notation:
+
+ *<name><tag0><tag1>...*
+
+Where:
+
+* *name* is a link to a description of the operand.
+* *tags* are optional. They are used to indicate special operand properties:
+
+.. _amdgpu_syn_instruction_operand_tags:
+
+ ============== =================================================================================
+ Operand tag Meaning
+ ============== =================================================================================
+ :opt An optional operand.
+ :m An operand which may be used with
+ :ref:`VOP3 operand modifiers<amdgpu_synid_vop3_operand_modifiers>` or
+ :ref:`SDWA operand modifiers<amdgpu_synid_sdwa_operand_modifiers>`.
+ :dst An input operand which may also serve as a destination
+ if :ref:`glc<amdgpu_synid_glc>` modifier is specified.
+ :fx This is an *f32* or *f16* operand depending on
+ :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` modifier.
+ :<type> Operand *type* differs from *type*
+ :ref:`implied by the opcode name<amdgpu_syn_instruction_type>`.
+ This tag specifies actual operand *type*.
+ ============== =================================================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ src1:m // src1 operand may be used with operand modifiers
+ vdata:dst // vdata operand may be used as both source and destination
+ vdst:u32 // vdst operand has u32 type
+
+.. _amdgpu_syn_instruction_modifiers_notation:
+
+Modifiers
+=========
+
+An instruction may have zero or more optional *modifiers*. They are space-separated in the description:
+
+ ``<``\ :ref:`description of modifier 0<amdgpu_syn_instruction_modifier_notation>`\ ``> <``\ :ref:`description of modifier 1<amdgpu_syn_instruction_modifier_notation>`\ ``> ...``
+
+The order of *modifiers* is fixed.
+
+.. _amdgpu_syn_instruction_modifier_notation:
+
+Notation
+~~~~~~~~
+
+A *modifier* is described using the following notation:
+
+ *<name>*
+
+Where *name* is a link to a description of the *modifier*.
Added: llvm/trunk/docs/AMDGPUInstructionSyntax.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUInstructionSyntax.rst?rev=349368&view=auto
==============================================================================
--- llvm/trunk/docs/AMDGPUInstructionSyntax.rst (added)
+++ llvm/trunk/docs/AMDGPUInstructionSyntax.rst Mon Dec 17 09:38:11 2018
@@ -0,0 +1,170 @@
+=========================
+AMDGPU Instruction Syntax
+=========================
+
+.. contents::
+ :local:
+
+.. _amdgpu_syn_instructions:
+
+Instructions
+============
+
+Syntax
+~~~~~~
+
+An instruction has the following syntax:
+
+ ``<``\ *opcode mnemonic*\ ``> <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,... <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
+
+:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while
+:doc:`modifiers<AMDGPUModifierSyntax>` are space-separated.
+
+The order of *operands* and *modifiers* is fixed.
+Most *modifiers* are optional and may be omitted.
+
+.. _amdgpu_syn_instruction_mnemo:
+
+Opcode Mnemonic
+~~~~~~~~~~~~~~~
+
+Opcode mnemonic describes opcode semantics and may include one or more suffices in this order:
+
+* :ref:`Destination operand type suffix<amdgpu_syn_instruction_type>`.
+* :ref:`Source operand type suffix<amdgpu_syn_instruction_type>`.
+* :ref:`Encoding suffix<amdgpu_syn_instruction_enc>`.
+
+.. _amdgpu_syn_instruction_type:
+
+Type and Size Suffices
+~~~~~~~~~~~~~~~~~~~~~~
+
+Instructions which operate with data have an implied type of *data* operands.
+This data type is specified as a suffix of instruction mnemonic.
+
+There are instructions which have 2 type suffices:
+the first is the data type of the destination operand,
+the second is the data type of source *data* operand(s).
+
+Note that data type specified by an instruction does not apply
+to other kinds of operands such as *addresses*, *offsets* and so on.
+
+The following table enumerates the most frequently used type suffices.
+
+ ============================================ ======================= =================
+ Type Suffices Packed instruction? Data Type
+ ============================================ ======================= =================
+ _b512, _b256, _b128, _b64, _b32, _b16, _b8 No Bits.
+ _u64, _u32, _u16, _u8 No Unsigned integer.
+ _i64, _i32, _i16, _i8 No Signed integer.
+ _f64, _f32, _f16 No Floating-point.
+ _b16, _u16, _i16, _f16 Yes Packed.
+ ============================================ ======================= =================
+
+Instructions which have no type suffices are assumed to operate with typeless data.
+The size of data is specified by size suffices:
+
+ ================= =================== =====================================
+ Size Suffix Implied data type Required register size in dwords
+ ================= =================== =====================================
+ \- b32 1
+ x2 b64 2
+ x3 b96 3
+ x4 b128 4
+ x8 b256 8
+ x16 b512 16
+ x b32 1
+ xy b64 2
+ xyz b96 3
+ xyzw b128 4
+ d16_x b16 1
+ d16_xy b16x2 2 for GFX8.0, 1 for GFX8.1 and GFX9
+ d16_xyz b16x3 3 for GFX8.0, 2 for GFX8.1 and GFX9
+ d16_xyzw b16x4 4 for GFX8.0, 2 for GFX8.1 and GFX9
+ ================= =================== =====================================
+
+.. WARNING::
+ There are exceptions from rules described above.
+ Operands which have type different from type specified by the opcode are
+ :ref:`tagged<amdgpu_syn_instruction_operand_tags>` in the description.
+
+Examples of instructions with different types of source and destination operands:
+
+.. code-block:: nasm
+
+ s_bcnt0_i32_b64
+ v_cvt_f32_u32
+
+Examples of instructions with one data type:
+
+.. code-block:: nasm
+
+ v_max3_f32
+ v_max3_i16
+
+Examples of instructions which operate with packed data:
+
+.. code-block:: nasm
+
+ v_pk_add_u16
+ v_pk_add_i16
+ v_pk_add_f16
+
+Examples of typeless instructions which operate on b128 data:
+
+.. code-block:: nasm
+
+ buffer_store_dwordx4
+ flat_load_dwordx4
+
+.. _amdgpu_syn_instruction_enc:
+
+Encoding Suffices
+~~~~~~~~~~~~~~~~~
+
+Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
+they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
+
+The assembler will automatically use optimal encoding based on instruction operands.
+To force specific encoding, one can add a suffix to the opcode of the instruction:
+
+ =================================================== =================
+ Encoding Encoding Suffix
+ =================================================== =================
+ Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32
+ *VOP3* (64-bit) encoding _e64
+ *DPP* encoding _dpp
+ *SDWA* encoding _sdwa
+ =================================================== =================
+
+These suffices are used in this reference to indicate the assumed encoding.
+When no suffix is specified, a native encoding is implied.
+
+Operands
+========
+
+Syntax
+~~~~~~
+
+Syntax of most operands is described :doc:`in this document<AMDGPUOperandSyntax>`.
+
+For detailed information about operands follow *operand links* in GPU-specific documents:
+
+* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
+* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
+* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+
+Modifiers
+=========
+
+Syntax
+~~~~~~
+
+Syntax of modifiers is described :doc:`in this document<AMDGPUModifierSyntax>`.
+
+Information about modifiers supported for individual instructions may be found in GPU-specific documents:
+
+* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
+* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
+* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+
Copied: llvm/trunk/docs/AMDGPUModifierSyntax.rst (from r349354, llvm/trunk/docs/AMDGPUOperandSyntax.rst)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUModifierSyntax.rst?p2=llvm/trunk/docs/AMDGPUModifierSyntax.rst&p1=llvm/trunk/docs/AMDGPUOperandSyntax.rst&r1=349354&r2=349368&rev=349368&view=diff
==============================================================================
--- llvm/trunk/docs/AMDGPUOperandSyntax.rst (original)
+++ llvm/trunk/docs/AMDGPUModifierSyntax.rst Mon Dec 17 09:38:11 2018
@@ -1,6 +1,6 @@
-=================================================
-Syntax of AMDGPU Assembler Operands and Modifiers
-=================================================
+======================================
+Syntax of AMDGPU Instruction Modifiers
+======================================
.. contents::
:local:
@@ -8,24 +8,15 @@ Syntax of AMDGPU Assembler Operands and
Conventions
===========
-The following conventions are used in syntax description:
+The following notation is used throughout this document:
=================== =============================================================
Notation Description
=================== =============================================================
{0..N} Any integer value in the range from 0 to N (inclusive).
- Unless stated otherwise, this value may be specified as
- either a literal or an llvm expression.
- <x> Syntax and meaning of *<x>* is explained elsewhere.
+ <x> Syntax and meaning of *x* is explained elsewhere.
=================== =============================================================
-.. _amdgpu_syn_operands:
-
-Operands
-========
-
-TBD
-
.. _amdgpu_syn_modifiers:
Modifiers
@@ -43,11 +34,19 @@ Specifies an immediate unsigned 8-bit of
Used with DS instructions which have 2 addresses.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..0xFF} Specifies a 8-bit offset.
- ======================================== ================================================
+ =================== =====================================================
+ Syntax Description
+ =================== =====================================================
+ offset:{0..0xFF} Specifies an unsigned 8-bit offset as a positive
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+ =================== =====================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ offset:255
+ offset:0xff
.. _amdgpu_synid_ds_offset16:
@@ -58,11 +57,19 @@ Specifies an immediate unsigned 16-bit o
Used with DS instructions which have 1 address.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..0xFFFF} Specifies a 16-bit offset.
- ======================================== ================================================
+ ==================== ======================================================
+ Syntax Description
+ ==================== ======================================================
+ offset:{0..0xFFFF} Specifies an unsigned 16-bit offset as a positive
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+ ==================== ======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ offset:65535
+ offset:0xffff
.. _amdgpu_synid_sw_offset16:
@@ -70,34 +77,38 @@ sw_offset16
~~~~~~~~~~~
This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
-Specifies a sizzle pattern in numeric or symbolic form. The default value is 0.
+It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.
See AMD documentation for more information.
- ======================================================= ===================================================
+ ======================================================= ===========================================================
Syntax Description
- ======================================================= ===================================================
- offset:{0..0xFFFF} Specifies a 16-bit swizzle pattern
- in a numeric form.
- offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3}) Specifies a quad permute mode pattern; each
- number is a lane id.
- offset:swizzle(BITMASK_PERM, "<mask>") Specifies a bitmask permute mode pattern
- which converts a 5-bit lane id to another
- lane id with which the lane interacts.
+ ======================================================= ===========================================================
+ offset:{0..0xFFFF} Specifies a 16-bit swizzle pattern.
+ offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3}) Specifies a quad permute mode pattern
+
+ Each number is a lane *id*.
+ offset:swizzle(BITMASK_PERM, "<mask>") Specifies a bitmask permute mode pattern.
- <mask> is a 5 character sequence which
+ The pattern converts a 5-bit lane *id* to another
+ lane *id* with which the lane interacts.
+
+ *mask* is a 5 character sequence which
specifies how to transform the bits of the
- lane id. The following characters are allowed:
+ lane *id*.
+
+ The following characters are allowed:
- * "0" - set bit to 0.
+ * "0" - set bit to 0.
- * "1" - set bit to 1.
+ * "1" - set bit to 1.
- * "p" - preserve bit.
+ * "p" - preserve bit.
- * "i" - inverse bit.
+ * "i" - inverse bit.
offset:swizzle(BROADCAST,{2..32},{0..N}) Specifies a broadcast mode.
+
Broadcasts the value of any particular lane to
all lanes in its group.
@@ -105,14 +116,32 @@ See AMD documentation for more informati
size and must be equal to 2, 4, 8, 16 or 32.
The second numeric parameter is an index of the
- lane being broadcasted. The index must not exceed
- group size.
+ lane being broadcasted.
+
+ The index must not exceed group size.
offset:swizzle(SWAP,{1..16}) Specifies a swap mode.
+
Swaps the neighboring groups of
1, 2, 4, 8 or 16 lanes.
- offset:swizzle(REVERSE,{2..32}) Specifies a reverse mode. Reverses
- the lanes for groups of 2, 4, 8, 16 or 32 lanes.
- ======================================================= ===================================================
+ offset:swizzle(REVERSE,{2..32}) Specifies a reverse mode.
+
+ Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.
+ ======================================================= ===========================================================
+
+Numeric parameters may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. code-block:: nasm
+
+ offset:255
+ offset:0xffff
+ offset:swizzle(QUAD_PERM, 0, 1, 2 ,3)
+ offset:swizzle(BITMASK_PERM, "01pi0")
+ offset:swizzle(BROADCAST, 2, 0)
+ offset:swizzle(SWAP, 8)
+ offset:swizzle(REVERSE, 30 + 2)
.. _amdgpu_synid_gds:
@@ -150,7 +179,7 @@ instruction does not finish an export se
compr
~~~~~
-Indicates if the data are compressed (not compressed by default).
+Indicates if the data are compressed (data are not compressed by default).
======================================== ================================================
Syntax Description
@@ -183,11 +212,19 @@ Specifies an immediate unsigned 12-bit o
Cannot be used with *global/scratch* opcodes. GFX9 only.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..4095} Specifies a 12-bit unsigned offset.
- ======================================== ================================================
+ ================= ======================================================
+ Syntax Description
+ ================= ======================================================
+ offset:{0..4095} Specifies a 12-bit unsigned offset as a positive
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+ ================= ======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ offset:4095
+ offset:0xff
.. _amdgpu_synid_flat_offset13:
@@ -198,11 +235,19 @@ Specifies an immediate signed 13-bit off
Can be used with *global/scratch* opcodes only. GFX9 only.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{-4096..+4095} Specifies a 13-bit signed offset.
- ======================================== ================================================
+ ============================ =======================================================
+ Syntax Description
+ ============================ =======================================================
+ offset:{-4096..+4095} Specifies a 13-bit signed offset as an
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+ ============================ =======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ offset:-4000
+ offset:0x10
glc
~~~
@@ -235,40 +280,53 @@ dmask
Specifies which channels (image components) are used by the operation. By default, no channels
are used.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- dmask:{0..15} Each bit corresponds to one of 4 image
- components (RGBA). If the specified bit value
- is 0, the component is not used, value 1 means
- that the component is used.
- ======================================== ================================================
+ =============== =====================================================
+ Syntax Description
+ =============== =====================================================
+ dmask:{0..15} Specifies image channels as a positive
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+
+ Each bit corresponds to one of 4 image
+ components (RGBA).
+
+ If the specified bit value
+ is 0, the component is not used, value 1 means
+ that the component is used.
+ =============== =====================================================
This modifier has some limitations depending on instruction kind:
- ======================================== ================================================
- Instruction Kind Valid dmask Values
- ======================================== ================================================
- 32-bit atomic cmpswap 0x3
- other 32-bit atomic instructions 0x1
- 64-bit atomic cmpswap 0xF
- other 64-bit atomic instructions 0x3
- GATHER4 0x1, 0x2, 0x4, 0x8
- Other instructions any value
- ======================================== ================================================
+ =================================================== ========================
+ Instruction Kind Valid dmask Values
+ =================================================== ========================
+ 32-bit atomic *cmpswap* 0x3
+ 32-bit atomic instructions except for *cmpswap* 0x1
+ 64-bit atomic *cmpswap* 0xF
+ 64-bit atomic instructions except for *cmpswap* 0x3
+ *gather4* 0x1, 0x2, 0x4, 0x8
+ Other instructions any value
+ =================================================== ========================
+
+Examples:
+
+.. code-block:: nasm
+
+ dmask:0xf
+ dmask:0b1111
+ dmask:3
.. _amdgpu_synid_unorm:
unorm
~~~~~
-Specifies whether address is normalized or not (normalized by default).
+Specifies whether the address is normalized or not (the address is normalized by default).
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- unorm Force address to be un-normalized.
- ======================================== ================================================
+ ======================== ========================================
+ Syntax Description
+ ======================== ========================================
+ unorm Force the address to be unnormalized.
+ ======================== ========================================
glc
~~~
@@ -289,11 +347,13 @@ Specifies texture resource size. The def
GFX7 and GFX8 only.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- r128 Specifies 128 bits texture resource size.
- ======================================== ================================================
+ =================== ================================================
+ Syntax Description
+ =================== ================================================
+ r128 Specifies 128 bits texture resource size.
+ =================== ================================================
+
+.. WARNING:: Using this modifier should descrease *rsrc* register size from 8 to 4 dwords, but assembler does not currently support this feature.
tfe
~~~
@@ -344,9 +404,12 @@ Specifies data size: 16 or 32 bits (32 b
For stores, convert 16-bit data in VGPRs to
32 bits before going to memory.
- Note that 16-bit data are stored in VGPRs
- unpacked in GFX8.0. In GFX8.1 and GFX9 16-bit
- data are packed.
+ Note that GFX8.0 does not support data packing.
+ Each 16-bit data element occupies 1 VGPR.
+
+ GFX8.1 and GFX9 support data packing.
+ Each pair of 16-bit data elements
+ occupies 1 VGPR.
======================================== ================================================
.. _amdgpu_synid_a16:
@@ -487,11 +550,19 @@ buf_offset12
Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..0xFFF} Specifies a 12-bit unsigned offset.
- ======================================== ================================================
+ =============================== ======================================================
+ Syntax Description
+ =============================== ======================================================
+ offset:{0..0xFFF} Specifies a 12-bit unsigned offset as a positive
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+ =============================== ======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ offset:0
+ offset:0x10
glc
~~~
@@ -510,11 +581,11 @@ lds
Specifies where to store the result: VGPRs or LDS (VGPRs by default).
- ======================================== ================================================
+ ======================================== ===========================
Syntax Description
- ======================================== ================================================
+ ======================================== ===========================
lds Store result in LDS.
- ======================================== ================================================
+ ======================================== ===========================
tfe
~~~
@@ -559,11 +630,11 @@ high
Specifies which half of the LDS word to use. Low half of LDS word is used by default.
GFX9 only.
- ======================================== ================================================
+ ======================================== ================================
Syntax Description
- ======================================== ================================================
+ ======================================== ================================
high Use high half of LDS word.
- ======================================== ================================================
+ ======================================== ================================
VOP1/VOP2 DPP Modifiers
-----------------------
@@ -597,6 +668,17 @@ Note. The lanes of a wavefront are organ
row_ror:{1..15} Row rotate right by 1-15 threads.
======================================== ================================================
+Note: Numeric parameters may be specified as either
+:ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. code-block:: nasm
+
+ quad_perm:[0, 1, 2, 3]
+ row_shl:3
+
.. _amdgpu_synid_row_mask:
row_mask
@@ -606,12 +688,23 @@ Controls which rows are enabled for data
Note. The lanes of a wavefront are organized in four banks and four rows.
- ======================================== ================================================
+ ======================================== =====================================================
Syntax Description
- ======================================== ================================================
- row_mask:{0..15} Each of 4 bits in the mask controls one
+ ======================================== =====================================================
+ row_mask:{0..15} Specifies a *row mask* as a positive
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+
+ Each of 4 bits in the mask controls one
row (0 - disabled, 1 - enabled).
- ======================================== ================================================
+ ======================================== =====================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ row_mask:0xf
+ row_mask:0b1010
+ row_mask:0b1111
.. _amdgpu_synid_bank_mask:
@@ -622,12 +715,23 @@ Controls which banks are enabled for dat
Note. The lanes of a wavefront are organized in four banks and four rows.
- ======================================== ================================================
+ ======================================== =======================================================
Syntax Description
- ======================================== ================================================
- bank_mask:{0..15} Each of 4 bits in the mask controls one
+ ======================================== =======================================================
+ bank_mask:{0..15} Specifies a *bank mask* as a positive
+ :ref:`integer number <amdgpu_synid_integer_number>`.
+
+ Each of 4 bits in the mask controls one
bank (0 - disabled, 1 - enabled).
- ======================================== ================================================
+ ======================================== =======================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ bank_mask:0x3
+ bank_mask:0b0011
+ bank_mask:0b1111
.. _amdgpu_synid_bound_ctrl:
@@ -641,6 +745,7 @@ invalid lanes is disabled.
Syntax Description
======================================== ================================================
bound_ctrl:0 Enables data sharing with invalid lanes.
+
Accessing data from an invalid lane will
return zero.
======================================== ================================================
@@ -737,6 +842,8 @@ Controls which bits in the src1 are used
src1_sel:WORD_1 Use bits 31:16.
======================================== ================================================
+.. _amdgpu_synid_sdwa_operand_modifiers:
+
VOP1/VOP2/VOPC SDWA Operand Modifiers
-------------------------------------
@@ -770,6 +877,13 @@ Valid for integer operands only.
sext(<operand>) Sign-extend operand value.
======================================== ================================================
+Examples:
+
+.. code-block:: nasm
+
+ sext(v4)
+ sext(v255)
+
VOP3 Modifiers
--------------
@@ -799,6 +913,13 @@ GFX9 only.
op_sel:[{0..1},{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
======================================== ============================================================
+Examples:
+
+.. code-block:: nasm
+
+ op_sel:[0,0]
+ op_sel:[0,1]
+
.. _amdgpu_synid_clamp:
clamp
@@ -849,6 +970,8 @@ but accepts output modifiers.
div:2 Multiply the result by 0.5.
======================================== ================================================
+.. _amdgpu_synid_vop3_operand_modifiers:
+
VOP3 Operand Modifiers
----------------------
@@ -869,6 +992,13 @@ Valid for floating point operands only.
\|<operand>| The same as above.
======================================== ================================================
+Examples:
+
+.. code-block:: nasm
+
+ abs(v36)
+ |v36|
+
.. _amdgpu_synid_neg:
neg
@@ -884,11 +1014,20 @@ Valid for floating point operands only.
-<operand> The same as above.
======================================== ================================================
+Examples:
+
+.. code-block:: nasm
+
+ neg(v[0])
+ -v4
+
VOP3P Modifiers
---------------
-This section describes modifiers of regular VOP3P instructions.
-*v_mad_mix* modifiers are described :ref:`in a separate section<amdgpu_synid_mad_mix>`.
+This section describes modifiers of *regular* VOP3P instructions.
+
+*v_mad_mix_f32*, *v_mad_mixhi_f16* and *v_mad_mixlo_f16*
+instructions use these modifiers :ref:`in a special manner<amdgpu_synid_mad_mix>`.
GFX9 only.
@@ -901,17 +1040,25 @@ Selects the low [15:0] or high [31:16] o
which results in the lower-half of the destination.
By default, low bits are used for all operands.
-The number of values specified with the op_sel modifier must match the number of source
+The number of values specified by the *op_sel* modifier must match the number of source
operands. First value controls src0, second value controls src1 and so on.
+
The value 0 selects the low bits, while 1 selects the high bits.
- ======================================== =============================================================
- Syntax Description
- ======================================== =============================================================
- op_sel:[{0..1}] Select operand bits for instructions with 1 source operand.
- op_sel:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
- op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
- ======================================== =============================================================
+ ================================= =============================================================
+ Syntax Description
+ ================================= =============================================================
+ op_sel:[{0..1}] Select operand bits for instructions with 1 source operand.
+ op_sel:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
+ op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
+ ================================= =============================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ op_sel:[0,0]
+ op_sel:[0,1,0]
.. _amdgpu_synid_op_sel_hi:
@@ -922,17 +1069,25 @@ Selects the low [15:0] or high [31:16] o
which results in the upper-half of the destination.
By default, high bits are used for all operands.
-The number of values specified with the op_sel_hi modifier must match the number of source
+The number of values specified by the *op_sel_hi* modifier must match the number of source
operands. First value controls src0, second value controls src1 and so on.
+
The value 0 selects the low bits, while 1 selects the high bits.
- ======================================== =============================================================
- Syntax Description
- ======================================== =============================================================
- op_sel_hi:[{0..1}] Select operand bits for instructions with 1 source operand.
- op_sel_hi:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
- op_sel_hi:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
- ======================================== =============================================================
+ =================================== =============================================================
+ Syntax Description
+ =================================== =============================================================
+ op_sel_hi:[{0..1}] Select operand bits for instructions with 1 source operand.
+ op_sel_hi:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
+ op_sel_hi:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
+ =================================== =============================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ op_sel_hi:[0,0]
+ op_sel_hi:[0,0,1]
.. _amdgpu_synid_neg_lo:
@@ -943,7 +1098,7 @@ Specifies whether to change sign of oper
:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used
as input to the operation which results in the upper-half of the destination.
-The number of values specified with this modifier must match the number of source
+The number of values specified by this modifier must match the number of source
operands. First value controls src0, second value controls src1 and so on.
The value 0 indicates that the corresponding operand value is used unmodified,
@@ -953,13 +1108,20 @@ By default, operand values are used unmo
This modifier is valid for floating point operands only.
- ======================================== ==================================================================
- Syntax Description
- ======================================== ==================================================================
- neg_lo:[{0..1}] Select affected operands for instructions with 1 source operand.
- neg_lo:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
- neg_lo:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
- ======================================== ==================================================================
+ ================================ ==================================================================
+ Syntax Description
+ ================================ ==================================================================
+ neg_lo:[{0..1}] Select affected operands for instructions with 1 source operand.
+ neg_lo:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
+ neg_lo:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
+ ================================ ==================================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ neg_lo:[0]
+ neg_lo:[0,1]
.. _amdgpu_synid_neg_hi:
@@ -970,7 +1132,7 @@ Specifies whether to change sign of oper
:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used
as input to the operation which results in the upper-half of the destination.
-The number of values specified with this modifier must match the number of source
+The number of values specified by this modifier must match the number of source
operands. First value controls src0, second value controls src1 and so on.
The value 0 indicates that the corresponding operand value is used unmodified,
@@ -980,13 +1142,20 @@ By default, operand values are used unmo
This modifier is valid for floating point operands only.
- ======================================== ==================================================================
- Syntax Description
- ======================================== ==================================================================
- neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand.
- neg_hi:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
- neg_hi:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
- ======================================== ==================================================================
+ =============================== ==================================================================
+ Syntax Description
+ =============================== ==================================================================
+ neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand.
+ neg_hi:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
+ neg_hi:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
+ =============================== ==================================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ neg_hi:[1,0]
+ neg_hi:[0,1,1]
clamp
~~~~~
@@ -998,7 +1167,11 @@ See a description :ref:`here<amdgpu_syni
VOP3P V_MAD_MIX Modifiers
-------------------------
-These instructions use VOP3P format but have different modifiers.
+*v_mad_mix_f32*, *v_mad_mixhi_f16* and *v_mad_mixlo_f16* instructions
+use *op_sel* and *op_sel_hi* modifiers
+in a manner different from *regular* VOP3P instructions.
+
+See a description below.
GFX9 only.
@@ -1012,14 +1185,24 @@ This operand has meaning only for 16-bit
It specifies to select either the low [15:0] or high [31:16] operand bits
as input to the operation.
+The number of values specified by the *op_sel* modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
+
By default, low bits are used for all operands.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- op_sel:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand.
- ======================================== ================================================
+ =============================== ================================================
+ Syntax Description
+ =============================== ================================================
+ op_sel:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand.
+ =============================== ================================================
+
+Examples:
+
+.. code-block:: nasm
+
+ op_sel:[0,1]
.. _amdgpu_synid_mad_mix_op_sel_hi:
@@ -1029,15 +1212,25 @@ mad_mix_op_sel_hi
Selects the size of source operands: either 32 bits or 16 bits.
By default, 32 bits are used for all source operands.
+The number of values specified by the *op_sel_hi* modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
The value 0 indicates 32 bits, the value 1 indicates 16 bits.
+
The location of 16 bits in the operand may be specified by
:ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>`.
- ======================================== ================================================
+ ======================================== ====================================
Syntax Description
- ======================================== ================================================
+ ======================================== ====================================
op_sel_hi:[{0..1},{0..1},{0..1}] Select size of each source operand.
- ======================================== ================================================
+ ======================================== ====================================
+
+Examples:
+
+.. code-block:: nasm
+
+ op_sel_hi:[1,1,1]
abs
~~~
Modified: llvm/trunk/docs/AMDGPUOperandSyntax.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUOperandSyntax.rst?rev=349368&r1=349367&r2=349368&view=diff
==============================================================================
--- llvm/trunk/docs/AMDGPUOperandSyntax.rst (original)
+++ llvm/trunk/docs/AMDGPUOperandSyntax.rst Mon Dec 17 09:38:11 2018
@@ -1,6 +1,6 @@
-=================================================
-Syntax of AMDGPU Assembler Operands and Modifiers
-=================================================
+=====================================
+Syntax of AMDGPU Instruction Operands
+=====================================
.. contents::
:local:
@@ -8,1048 +8,1058 @@ Syntax of AMDGPU Assembler Operands and
Conventions
===========
-The following conventions are used in syntax description:
+The following notation is used throughout this document:
- =================== =============================================================
+ =================== =============================================================================
Notation Description
- =================== =============================================================
+ =================== =============================================================================
{0..N} Any integer value in the range from 0 to N (inclusive).
- Unless stated otherwise, this value may be specified as
- either a literal or an llvm expression.
- <x> Syntax and meaning of *<x>* is explained elsewhere.
- =================== =============================================================
+ <x> Syntax and meaning of *x* is explained elsewhere.
+ =================== =============================================================================
.. _amdgpu_syn_operands:
Operands
========
-TBD
+.. _amdgpu_synid_v:
-.. _amdgpu_syn_modifiers:
+v
+-
-Modifiers
-=========
+Vector registers. There are 256 32-bit vector registers.
-DS Modifiers
-------------
-
-.. _amdgpu_synid_ds_offset8:
-
-ds_offset8
-~~~~~~~~~~
-
-Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0.
-
-Used with DS instructions which have 2 addresses.
-
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..0xFF} Specifies a 8-bit offset.
- ======================================== ================================================
-
-.. _amdgpu_synid_ds_offset16:
-
-ds_offset16
-~~~~~~~~~~~
-
-Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0.
-
-Used with DS instructions which have 1 address.
-
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..0xFFFF} Specifies a 16-bit offset.
- ======================================== ================================================
-
-.. _amdgpu_synid_sw_offset16:
-
-sw_offset16
-~~~~~~~~~~~
-
-This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
-Specifies a sizzle pattern in numeric or symbolic form. The default value is 0.
-
-See AMD documentation for more information.
-
- ======================================================= ===================================================
- Syntax Description
- ======================================================= ===================================================
- offset:{0..0xFFFF} Specifies a 16-bit swizzle pattern
- in a numeric form.
- offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3}) Specifies a quad permute mode pattern; each
- number is a lane id.
- offset:swizzle(BITMASK_PERM, "<mask>") Specifies a bitmask permute mode pattern
- which converts a 5-bit lane id to another
- lane id with which the lane interacts.
+A sequence of *vector* registers may be used to operate with more than 32 bits of data.
- <mask> is a 5 character sequence which
- specifies how to transform the bits of the
- lane id. The following characters are allowed:
+Assembler currently supports sequences of 1, 2, 3, 4, 8 and 16 *vector* registers.
- * "0" - set bit to 0.
+ =================================================== ====================================================================
+ Syntax Description
+ =================================================== ====================================================================
+ **v**\<N> A single 32-bit *vector* register.
- * "1" - set bit to 1.
+ *N* must be a decimal integer number.
+ **v[**\ <N>\ **]** A single 32-bit *vector* register.
- * "p" - preserve bit.
+ *N* may be specified as an
+ :ref:`integer number<amdgpu_synid_integer_number>`
+ or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+ **v[**\ <N>:<K>\ **]** A sequence of (\ *K-N+1*\ ) *vector* registers.
- * "i" - inverse bit.
+ *N* and *K* may be specified as
+ :ref:`integer numbers<amdgpu_synid_integer_number>`
+ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+ **[v**\ <N>, \ **v**\ <N+1>, ... **v**\ <K>\ **]** A sequence of (\ *K-N+1*\ ) *vector* registers.
- offset:swizzle(BROADCAST,{2..32},{0..N}) Specifies a broadcast mode.
- Broadcasts the value of any particular lane to
- all lanes in its group.
+ Register indices must be specified as decimal integer numbers.
+ =================================================== ====================================================================
- The first numeric parameter is a group
- size and must be equal to 2, 4, 8, 16 or 32.
+Note. *N* and *K* must satisfy the following conditions:
- The second numeric parameter is an index of the
- lane being broadcasted. The index must not exceed
- group size.
- offset:swizzle(SWAP,{1..16}) Specifies a swap mode.
- Swaps the neighboring groups of
- 1, 2, 4, 8 or 16 lanes.
- offset:swizzle(REVERSE,{2..32}) Specifies a reverse mode. Reverses
- the lanes for groups of 2, 4, 8, 16 or 32 lanes.
- ======================================================= ===================================================
+* *N* <= *K*.
+* 0 <= *N* <= 255.
+* 0 <= *K* <= 255.
+* *K-N+1* must be equal to 1, 2, 3, 4, 8 or 16.
-.. _amdgpu_synid_gds:
+Examples:
-gds
-~~~
+.. code-block:: nasm
-Specifies whether to use GDS or LDS memory (LDS is the default).
+ v255
+ v[0]
+ v[0:1]
+ v[1:1]
+ v[0:3]
+ v[2*2]
+ v[1-1:2-1]
+ [v252]
+ [v252,v253,v254,v255]
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- gds Use GDS memory.
- ======================================== ================================================
+.. _amdgpu_synid_s:
+s
+-
-EXP Modifiers
--------------
+Scalar 32-bit registers. The number of available *scalar* registers depends on GPU:
-.. _amdgpu_synid_done:
+ ======= ============================
+ GPU Number of *scalar* registers
+ ======= ============================
+ GFX7 104
+ GFX8 102
+ GFX9 102
+ ======= ============================
-done
-~~~~
+A sequence of *scalar* registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 *scalar* registers.
-Specifies if this is the last export from the shader to the target. By default, current
-instruction does not finish an export sequence.
+Pairs of *scalar* registers must be even-aligned (the first register must be even).
+Sequences of 4 and more *scalar* registers must be quad-aligned.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- done Indicates the last export operation.
- ======================================== ================================================
+ ======================================================== ====================================================================
+ Syntax Description
+ ======================================================== ====================================================================
+ **s**\ <N> A single 32-bit *scalar* register.
-.. _amdgpu_synid_compr:
+ *N* must be a decimal integer number.
+ **s[**\ <N>\ **]** A single 32-bit *scalar* register.
-compr
-~~~~~
+ *N* may be specified as an
+ :ref:`integer number<amdgpu_synid_integer_number>`
+ or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+ **s[**\ <N>:<K>\ **]** A sequence of (\ *K-N+1*\ ) *scalar* registers.
-Indicates if the data are compressed (not compressed by default).
+ *N* and *K* may be specified as
+ :ref:`integer numbers<amdgpu_synid_integer_number>`
+ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+ **[s**\ <N>, \ **s**\ <N+1>, ... **s**\ <K>\ **]** A sequence of (\ *K-N+1*\ ) *scalar* registers.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- compr Data are compressed.
- ======================================== ================================================
+ Register indices must be specified as decimal integer numbers.
+ ======================================================== ====================================================================
-.. _amdgpu_synid_vm:
+Note. *N* and *K* must satisfy the following conditions:
-vm
-~~
+* *N* must be properly aligned based on sequence size.
+* *N* <= *K*.
+* 0 <= *N* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
+* 0 <= *K* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
+* *K-N+1* must be equal to 1, 2, 4, 8 or 16.
-Specifies valid mask flag state (off by default).
+Examples:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- vm Set valid mask flag.
- ======================================== ================================================
+.. code-block:: nasm
-FLAT Modifiers
---------------
+ s0
+ s[0]
+ s[0:1]
+ s[1:1]
+ s[0:3]
+ s[2*2]
+ s[1-1:2-1]
+ [s4]
+ [s4,s5,s6,s7]
-.. _amdgpu_synid_flat_offset12:
+Examples of *scalar* registers with an invalid alignment:
-flat_offset12
-~~~~~~~~~~~~~
+.. code-block:: nasm
-Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+ s[1:2]
+ s[2:5]
-Cannot be used with *global/scratch* opcodes. GFX9 only.
+.. _amdgpu_synid_trap:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..4095} Specifies a 12-bit unsigned offset.
- ======================================== ================================================
+trap
+----
-.. _amdgpu_synid_flat_offset13:
+A set of trap handler registers:
-flat_offset13
-~~~~~~~~~~~~~
+* :ref:`ttmp<amdgpu_synid_ttmp>`
+* :ref:`tba<amdgpu_synid_tba>`
+* :ref:`tma<amdgpu_synid_tma>`
-Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.
+.. _amdgpu_synid_ttmp:
-Can be used with *global/scratch* opcodes only. GFX9 only.
+ttmp
+----
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{-4096..+4095} Specifies a 13-bit signed offset.
- ======================================== ================================================
+Trap handler temporary scalar registers, 32-bits wide.
+The number of available *ttmp* registers depends on GPU:
-glc
-~~~
+ ======= ===========================
+ GPU Number of *ttmp* registers
+ ======= ===========================
+ GFX7 12
+ GFX8 12
+ GFX9 16
+ ======= ===========================
-See a description :ref:`here<amdgpu_synid_glc>`.
+A sequence of *ttmp* registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 *ttmp* registers.
-slc
-~~~
+Pairs of *ttmp* registers must be even-aligned (the first register must be even).
+Sequences of 4 and more *ttmp* registers must be quad-aligned.
-See a description :ref:`here<amdgpu_synid_slc>`.
+ ============================================================= ====================================================================
+ Syntax Description
+ ============================================================= ====================================================================
+ **ttmp**\ <N> A single 32-bit *ttmp* register.
-tfe
-~~~
+ *N* must be a decimal integer number.
+ **ttmp[**\ <N>\ **]** A single 32-bit *ttmp* register.
-See a description :ref:`here<amdgpu_synid_tfe>`.
+ *N* may be specified as an
+ :ref:`integer number<amdgpu_synid_integer_number>`
+ or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+ **ttmp[**\ <N>:<K>\ **]** A sequence of (\ *K-N+1*\ ) *ttmp* registers.
-nv
-~~
+ *N* and *K* may be specified as
+ :ref:`integer numbers<amdgpu_synid_integer_number>`
+ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+ **[ttmp**\ <N>, \ **ttmp**\ <N+1>, ... **ttmp**\ <K>\ **]** A sequence of (\ *K-N+1*\ ) *ttmp* registers.
-See a description :ref:`here<amdgpu_synid_nv>`.
+ Register indices must be specified as decimal integer numbers.
+ ============================================================= ====================================================================
-MIMG Modifiers
---------------
+Note. *N* and *K* must satisfy the following conditions:
-.. _amdgpu_synid_dmask:
+* *N* must be properly aligned based on sequence size.
+* *N* <= *K*.
+* 0 <= *N* < *TMAX*, where *TMAX* is the number of available *ttmp* registers.
+* 0 <= *K* < *TMAX*, where *TMAX* is the number of available *ttmp* registers.
+* *K-N+1* must be equal to 1, 2, 4, 8 or 16.
-dmask
-~~~~~
+Examples:
-Specifies which channels (image components) are used by the operation. By default, no channels
-are used.
+.. code-block:: nasm
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- dmask:{0..15} Each bit corresponds to one of 4 image
- components (RGBA). If the specified bit value
- is 0, the component is not used, value 1 means
- that the component is used.
- ======================================== ================================================
+ ttmp0
+ ttmp[0]
+ ttmp[0:1]
+ ttmp[1:1]
+ ttmp[0:3]
+ ttmp[2*2]
+ ttmp[1-1:2-1]
+ [ttmp4]
+ [ttmp4,ttmp5,ttmp6,ttmp7]
-This modifier has some limitations depending on instruction kind:
+Examples of *ttmp* registers with an invalid alignment:
- ======================================== ================================================
- Instruction Kind Valid dmask Values
- ======================================== ================================================
- 32-bit atomic cmpswap 0x3
- other 32-bit atomic instructions 0x1
- 64-bit atomic cmpswap 0xF
- other 64-bit atomic instructions 0x3
- GATHER4 0x1, 0x2, 0x4, 0x8
- Other instructions any value
- ======================================== ================================================
+.. code-block:: nasm
-.. _amdgpu_synid_unorm:
+ ttmp[1:2]
+ ttmp[2:5]
-unorm
-~~~~~
+.. _amdgpu_synid_tba:
-Specifies whether address is normalized or not (normalized by default).
+tba
+---
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- unorm Force address to be un-normalized.
- ======================================== ================================================
+Trap base address, 64-bits wide. Holds the pointer to the current trap handler program.
-glc
-~~~
+ ================== ======================================================================= =============
+ Syntax Description Availability
+ ================== ======================================================================= =============
+ tba 64-bit *trap base address* register. GFX7, GFX8
+ [tba] 64-bit *trap base address* register (an alternative syntax). GFX7, GFX8
+ [tba_lo,tba_hi] 64-bit *trap base address* register (an alternative syntax). GFX7, GFX8
+ ================== ======================================================================= =============
-See a description :ref:`here<amdgpu_synid_glc>`.
+High and low 32 bits of *trap base address* may be accessed as separate registers:
-slc
-~~~
+ ================== ======================================================================= =============
+ Syntax Description Availability
+ ================== ======================================================================= =============
+ tba_lo Low 32 bits of *trap base address* register. GFX7, GFX8
+ tba_hi High 32 bits of *trap base address* register. GFX7, GFX8
+ [tba_lo] Low 32 bits of *trap base address* register (an alternative syntax). GFX7, GFX8
+ [tba_hi] High 32 bits of *trap base address* register (an alternative syntax). GFX7, GFX8
+ ================== ======================================================================= =============
-See a description :ref:`here<amdgpu_synid_slc>`.
+Note that *tba*, *tba_lo* and *tba_hi* are not accessible as assembler registers in GFX9,
+but *tba* is readable/writable with the help of *s_get_reg* and *s_set_reg* instructions.
-.. _amdgpu_synid_r128:
+.. _amdgpu_synid_tma:
-r128
-~~~~
+tma
+---
-Specifies texture resource size. The default size is 256 bits.
+Trap memory address, 64-bits wide.
-GFX7 and GFX8 only.
+ ================= ======================================================================= ==================
+ Syntax Description Availability
+ ================= ======================================================================= ==================
+ tma 64-bit *trap memory address* register. GFX7, GFX8
+ [tma] 64-bit *trap memory address* register (an alternative syntax). GFX7, GFX8
+ [tma_lo,tma_hi] 64-bit *trap memory address* register (an alternative syntax). GFX7, GFX8
+ ================= ======================================================================= ==================
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- r128 Specifies 128 bits texture resource size.
- ======================================== ================================================
+High and low 32 bits of *trap memory address* may be accessed as separate registers:
-tfe
-~~~
+ ================= ======================================================================= ==================
+ Syntax Description Availability
+ ================= ======================================================================= ==================
+ tma_lo Low 32 bits of *trap memory address* register. GFX7, GFX8
+ tma_hi High 32 bits of *trap memory address* register. GFX7, GFX8
+ [tma_lo] Low 32 bits of *trap memory address* register (an alternative syntax). GFX7, GFX8
+ [tma_hi] High 32 bits of *trap memory address* register (an alternative syntax). GFX7, GFX8
+ ================= ======================================================================= ==================
-See a description :ref:`here<amdgpu_synid_tfe>`.
+Note that *tma*, *tma_lo* and *tma_hi* are not accessible as assembler registers in GFX9,
+but *tma* is readable/writable with the help of *s_get_reg* and *s_set_reg* instructions.
-.. _amdgpu_synid_lwe:
+.. _amdgpu_synid_flat_scratch:
-lwe
-~~~
+flat_scratch
+------------
-Specifies LOD warning status (LOD warning is disabled by default).
+Flat scratch address, 64-bits wide. Holds the base address of scratch memory.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- lwe Enables LOD warning.
- ======================================== ================================================
+ ================================== ================================================================
+ Syntax Description
+ ================================== ================================================================
+ flat_scratch 64-bit *flat scratch* address register.
+ [flat_scratch] 64-bit *flat scratch* address register (an alternative syntax).
+ [flat_scratch_lo,flat_scratch_hi] 64-bit *flat scratch* address register (an alternative syntax).
+ ================================== ================================================================
-.. _amdgpu_synid_da:
+High and low 32 bits of *flat scratch* address may be accessed as separate registers:
-da
-~~
+ ========================= =========================================================================
+ Syntax Description
+ ========================= =========================================================================
+ flat_scratch_lo Low 32 bits of *flat scratch* address register.
+ flat_scratch_hi High 32 bits of *flat scratch* address register.
+ [flat_scratch_lo] Low 32 bits of *flat scratch* address register (an alternative syntax).
+ [flat_scratch_hi] High 32 bits of *flat scratch* address register (an alternative syntax).
+ ========================= =========================================================================
-Specifies if an array index must be sent to TA. By default, array index is not sent.
+.. _amdgpu_synid_xnack:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- da Send an array-index to TA.
- ======================================== ================================================
+xnack
+-----
-.. _amdgpu_synid_d16:
+Xnack mask, 64-bits wide. Holds a 64-bit mask of which threads
+received an *XNACK* due to a vector memory operation.
-d16
-~~~
+.. WARNING:: GFX7 does not support *xnack* feature. Not all GFX8 and GFX9 :ref:`processors<amdgpu-processors>` support *xnack* feature.
-Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.
+\
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- d16 Enables 16-bits data mode.
+ ============================== =====================================================
+ Syntax Description
+ ============================== =====================================================
+ xnack_mask 64-bit *xnack mask* register.
+ [xnack_mask] 64-bit *xnack mask* register (an alternative syntax).
+ [xnack_mask_lo,xnack_mask_hi] 64-bit *xnack mask* register (an alternative syntax).
+ ============================== =====================================================
- On loads, convert data in memory to 16-bit
- format before storing it in VGPRs.
+High and low 32 bits of *xnack mask* may be accessed as separate registers:
- For stores, convert 16-bit data in VGPRs to
- 32 bits before going to memory.
+ ===================== ==============================================================
+ Syntax Description
+ ===================== ==============================================================
+ xnack_mask_lo Low 32 bits of *xnack mask* register.
+ xnack_mask_hi High 32 bits of *xnack mask* register.
+ [xnack_mask_lo] Low 32 bits of *xnack mask* register (an alternative syntax).
+ [xnack_mask_hi] High 32 bits of *xnack mask* register (an alternative syntax).
+ ===================== ==============================================================
- Note that 16-bit data are stored in VGPRs
- unpacked in GFX8.0. In GFX8.1 and GFX9 16-bit
- data are packed.
- ======================================== ================================================
+.. _amdgpu_synid_vcc:
-.. _amdgpu_synid_a16:
+vcc
+---
-a16
-~~~
+Vector condition code, 64-bits wide. A bit mask with one bit per thread;
+it holds the result of a vector compare operation.
-Specifies size of image address components: 16 or 32 bits (32 bits by default). GFX9 only.
+ ================ =========================================================================
+ Syntax Description
+ ================ =========================================================================
+ vcc 64-bit *vector condition code* register.
+ [vcc] 64-bit *vector condition code* register (an alternative syntax).
+ [vcc_lo,vcc_hi] 64-bit *vector condition code* register (an alternative syntax).
+ ================ =========================================================================
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- a16 Enables 16-bits image address components.
- ======================================== ================================================
+High and low 32 bits of *vector condition code* may be accessed as separate registers:
-Miscellaneous Modifiers
------------------------
+ ================ =========================================================================
+ Syntax Description
+ ================ =========================================================================
+ vcc_lo Low 32 bits of *vector condition code* register.
+ vcc_hi High 32 bits of *vector condition code* register.
+ [vcc_lo] Low 32 bits of *vector condition code* register (an alternative syntax).
+ [vcc_hi] High 32 bits of *vector condition code* register (an alternative syntax).
+ ================ =========================================================================
-.. _amdgpu_synid_glc:
+.. _amdgpu_synid_m0:
-glc
-~~~
+m0
+--
-This modifier has different meaning for loads, stores, and atomic operations.
-The default value is off (0).
+A 32-bit memory register. It has various uses,
+including register indexing and bounds checking.
-See AMD documentation for details.
+ =========== ===================================================
+ Syntax Description
+ =========== ===================================================
+ m0 A 32-bit *memory* register.
+ [m0] A 32-bit *memory* register (an alternative syntax).
+ =========== ===================================================
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- glc Set glc bit to 1.
- ======================================== ================================================
+.. _amdgpu_synid_exec:
-.. _amdgpu_synid_slc:
+exec
+----
-slc
-~~~
+Execute mask, 64-bits wide. A bit mask with one bit per thread,
+which is applied to vector instructions and controls which threads execute
+and which ignore the instruction.
-Specifies cache policy. The default value is off (0).
+ ===================== =================================================================
+ Syntax Description
+ ===================== =================================================================
+ exec 64-bit *execute mask* register.
+ [exec] 64-bit *execute mask* register (an alternative syntax).
+ [exec_lo,exec_hi] 64-bit *execute mask* register (an alternative syntax).
+ ===================== =================================================================
-See AMD documentation for details.
+High and low 32 bits of *execute mask* may be accessed as separate registers:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- slc Set slc bit to 1.
- ======================================== ================================================
+ ===================== =================================================================
+ Syntax Description
+ ===================== =================================================================
+ exec_lo Low 32 bits of *execute mask* register.
+ exec_hi High 32 bits of *execute mask* register.
+ [exec_lo] Low 32 bits of *execute mask* register (an alternative syntax).
+ [exec_hi] High 32 bits of *execute mask* register (an alternative syntax).
+ ===================== =================================================================
-.. _amdgpu_synid_tfe:
+.. _amdgpu_synid_vccz:
-tfe
-~~~
+vccz
+----
-Controls access to partially resident textures. The default value is off (0).
+A single bit-flag indicating that the :ref:`vcc<amdgpu_synid_vcc>` is all zeros.
-See AMD documentation for details.
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- tfe Set tfe bit to 1.
- ======================================== ================================================
+.. _amdgpu_synid_execz:
-.. _amdgpu_synid_nv:
+execz
+-----
-nv
-~~
+A single bit flag indicating that the :ref:`exec<amdgpu_synid_exec>` is all zeros.
-Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
-GFX9 only.
+.. _amdgpu_synid_scc:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- nv Indicates that instruction operates on
- non-volatile memory.
- ======================================== ================================================
+scc
+---
-MUBUF/MTBUF Modifiers
----------------------
+A single bit flag indicating the result of a scalar compare operation.
-.. _amdgpu_synid_idxen:
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
-idxen
-~~~~~
+.. _amdgpu_synid_ldsdirect:
-Specifies whether address components include an index. By default, no components are used.
+lds_direct
+----------
-Can be used together with :ref:`offen<amdgpu_synid_offen>`.
+A special operand which supplies a 32-bit value
+fetched from *LDS* memory using :ref:`m0<amdgpu_synid_m0>` as an address.
-Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+.. WARNING:: This operand is not currently supported by AMDGPU assembler.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- idxen Address components include an index.
- ======================================== ================================================
+.. _amdgpu_synid_constant:
-.. _amdgpu_synid_offen:
+constant
+--------
-offen
-~~~~~
+A set of integer and floating-point *inline constants*:
-Specifies whether address components include an offset. By default, no components are used.
+* :ref:`iconst<amdgpu_synid_iconst>`
+* :ref:`fconst<amdgpu_synid_fconst>`
-Can be used together with :ref:`idxen<amdgpu_synid_idxen>`.
+These operands are encoded as a part of instruction.
-Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+If a number may be encoded as either
+a :ref:`literal<amdgpu_synid_literal>` or
+an :ref:`inline constant<amdgpu_synid_constant>`,
+assembler selects the latter encoding as more efficient.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offen Address components include an offset.
- ======================================== ================================================
+.. _amdgpu_synid_iconst:
-.. _amdgpu_synid_addr64:
+iconst
+------
-addr64
-~~~~~~
+An :ref:`integer number<amdgpu_synid_integer_number>`
+encoded as an *inline constant*.
-Specifies whether a 64-bit address is used. By default, no address is used.
+Only a small fraction of integer numbers may be encoded as *inline constants*.
+They are enumerated in the table below.
+Other integer numbers have to be encoded as :ref:`literals<amdgpu_synid_literal>`.
-GFX7 only. Cannot be used with :ref:`offen<amdgpu_synid_offen>` and
-:ref:`idxen<amdgpu_synid_idxen>` modifiers.
+Integer *inline constants* are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>`
+as described :ref:`here<amdgpu_synid_int_const_conv>`.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- addr64 A 64-bit address is used.
- ======================================== ================================================
+ ================================== ====================================
+ Value Note
+ ================================== ====================================
+ {0..64} Positive integer inline constants.
+ {-16..-1} Negative integer inline constants.
+ ================================== ====================================
-.. _amdgpu_synid_buf_offset12:
+.. WARNING:: GFX7 does not support inline constants for *f16* operands.
-buf_offset12
-~~~~~~~~~~~~
+There are also symbolic inline constants which provide read-only access to H/W registers.
-Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+.. WARNING:: These inline constants are not currently supported by AMDGPU assembler.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- offset:{0..0xFFF} Specifies a 12-bit unsigned offset.
- ======================================== ================================================
+\
-glc
-~~~
+ ======================== ================================================ =============
+ Syntax Note Availability
+ ======================== ================================================ =============
+ shared_base Base address of shared memory region. GFX9
+ shared_limit Address of the end of shared memory region. GFX9
+ private_base Base address of private memory region. GFX9
+ private_limit Address of the end of private memory region. GFX9
+ pops_exiting_wave_id A dedicated counter for POPS. GFX9
+ ======================== ================================================ =============
-See a description :ref:`here<amdgpu_synid_glc>`.
+.. _amdgpu_synid_fconst:
-slc
-~~~
+fconst
+------
-See a description :ref:`here<amdgpu_synid_slc>`.
+A :ref:`floating-point number<amdgpu_synid_floating-point_number>`
+encoded as an *inline constant*.
-.. _amdgpu_synid_lds:
+Only a small fraction of floating-point numbers may be encoded as *inline constants*.
+They are enumerated in the table below.
+Other floating-point numbers have to be encoded as :ref:`literals<amdgpu_synid_literal>`.
-lds
-~~~
+Floating-point *inline constants* are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>`
+as described :ref:`here<amdgpu_synid_fp_const_conv>`.
-Specifies where to store the result: VGPRs or LDS (VGPRs by default).
+ ================================== ===================================================== ==================
+ Value Note Availability
+ ================================== ===================================================== ==================
+ 0.0 The same as integer constant 0. All GPUs
+ 0.5 Floating-point constant 0.5 All GPUs
+ 1.0 Floating-point constant 1.0 All GPUs
+ 2.0 Floating-point constant 2.0 All GPUs
+ 4.0 Floating-point constant 4.0 All GPUs
+ -0.5 Floating-point constant -0.5 All GPUs
+ -1.0 Floating-point constant -1.0 All GPUs
+ -2.0 Floating-point constant -2.0 All GPUs
+ -4.0 Floating-point constant -4.0 All GPUs
+ 0.1592 1.0/(2.0*pi). Use only for 16-bit operands. GFX8, GFX9
+ 0.15915494 1.0/(2.0*pi). Use only for 16- and 32-bit operands. GFX8, GFX9
+ 0.159154943091895317852646485335 1.0/(2.0*pi). GFX8, GFX9
+ ================================== ===================================================== ==================
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- lds Store result in LDS.
- ======================================== ================================================
+.. WARNING:: GFX7 does not support inline constants for *f16* operands.
-tfe
-~~~
+.. _amdgpu_synid_literal:
-See a description :ref:`here<amdgpu_synid_tfe>`.
+literal
+-------
-.. _amdgpu_synid_dfmt:
+A literal is a 64-bit value which is encoded as a separate 32-bit dword in the instruction stream.
-dfmt
-~~~~
+If a number may be encoded as either
+a :ref:`literal<amdgpu_synid_literal>` or
+an :ref:`inline constant<amdgpu_synid_constant>`,
+assembler selects the latter encoding as more efficient.
-TBD
+Literals may be specified as :ref:`integer numbers<amdgpu_synid_integer_number>`,
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>` or
+:ref:`expressions<amdgpu_synid_expression>`
+(expressions are currently supported for 32-bit operands only).
-.. _amdgpu_synid_nfmt:
+A 64-bit literal value is converted by assembler
+to an :ref:`expected operand type<amdgpu_syn_instruction_type>`
+as described :ref:`here<amdgpu_synid_lit_conv>`.
-nfmt
-~~~~
+An instruction may use only one literal but several operands may refer the same literal.
-TBD
+.. _amdgpu_synid_uimm8:
-SMRD/SMEM Modifiers
--------------------
+uimm8
+-----
-glc
-~~~
+A 8-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
+The value is encoded as part of the opcode so it is free to use.
-See a description :ref:`here<amdgpu_synid_glc>`.
+.. _amdgpu_synid_uimm32:
-nv
-~~
+uimm32
+------
-See a description :ref:`here<amdgpu_synid_nv>`.
+A 32-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
+The value is stored as a separate 32-bit dword in the instruction stream.
-VINTRP Modifiers
-----------------
+.. _amdgpu_synid_uimm20:
-.. _amdgpu_synid_high:
+uimm20
+------
-high
-~~~~
+A 20-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
-Specifies which half of the LDS word to use. Low half of LDS word is used by default.
-GFX9 only.
+.. _amdgpu_synid_uimm21:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- high Use high half of LDS word.
- ======================================== ================================================
-
-VOP1/VOP2 DPP Modifiers
------------------------
+uimm21
+------
-GFX8 and GFX9 only.
+A 21-bit positive :ref:`integer number<amdgpu_synid_integer_number>`.
-.. _amdgpu_synid_dpp_ctrl:
+.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
-dpp_ctrl
-~~~~~~~~
+.. _amdgpu_synid_simm21:
-Specifies how data are shared between threads. This is a mandatory modifier.
-There is no default value.
+simm21
+------
-Note. The lanes of a wavefront are organized in four banks and four rows.
+A 21-bit :ref:`integer number<amdgpu_synid_integer_number>`.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
- row_mirror Mirror threads within row.
- row_half_mirror Mirror threads within 1/2 row (8 threads).
- row_bcast:15 Broadcast 15th thread of each row to next row.
- row_bcast:31 Broadcast thread 31 to rows 2 and 3.
- wave_shl:1 Wavefront left shift by 1 thread.
- wave_rol:1 Wavefront left rotate by 1 thread.
- wave_shr:1 Wavefront right shift by 1 thread.
- wave_ror:1 Wavefront right rotate by 1 thread.
- row_shl:{1..15} Row shift left by 1-15 threads.
- row_shr:{1..15} Row shift right by 1-15 threads.
- row_ror:{1..15} Row rotate right by 1-15 threads.
- ======================================== ================================================
+.. WARNING:: Assembler currently supports 20-bit unsigned offsets only .Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
-.. _amdgpu_synid_row_mask:
+.. _amdgpu_synid_off:
-row_mask
-~~~~~~~~
+off
+---
-Controls which rows are enabled for data sharing. By default, all rows are enabled.
+A special entity which indicates that the value of this operand is not used.
-Note. The lanes of a wavefront are organized in four banks and four rows.
+ ================================== ===================================================
+ Syntax Description
+ ================================== ===================================================
+ off Indicates an unused operand.
+ ================================== ===================================================
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- row_mask:{0..15} Each of 4 bits in the mask controls one
- row (0 - disabled, 1 - enabled).
- ======================================== ================================================
-.. _amdgpu_synid_bank_mask:
+.. _amdgpu_synid_number:
-bank_mask
-~~~~~~~~~
+Numbers
+=======
-Controls which banks are enabled for data sharing. By default, all banks are enabled.
+.. _amdgpu_synid_integer_number:
-Note. The lanes of a wavefront are organized in four banks and four rows.
-
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- bank_mask:{0..15} Each of 4 bits in the mask controls one
- bank (0 - disabled, 1 - enabled).
- ======================================== ================================================
+Integer Numbers
+---------------
-.. _amdgpu_synid_bound_ctrl:
+Integer numbers are 64 bits wide.
+They may be specified in binary, octal, hexadecimal and decimal formats:
-bound_ctrl
-~~~~~~~~~~
+ ============== ====================================
+ Format Syntax
+ ============== ====================================
+ Decimal [-]?[1-9][0-9]*
+ Binary [-]?0b[01]+
+ Octal [-]?0[0-7]+
+ Hexadecimal [-]?0x[0-9a-fA-F]+
+ \ [-]?[0x]?[0-9][0-9a-fA-F]*[hH]
+ ============== ====================================
+
+Examples:
+
+.. code-block:: nasm
+
+ -1234
+ 0b1010
+ 010
+ 0xff
+ 0ffh
-Controls data sharing when accessing an invalid lane. By default, data sharing with
-invalid lanes is disabled.
+.. _amdgpu_synid_floating-point_number:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- bound_ctrl:0 Enables data sharing with invalid lanes.
- Accessing data from an invalid lane will
- return zero.
- ======================================== ================================================
+Floating-Point Numbers
+----------------------
-VOP1/VOP2/VOPC SDWA Modifiers
------------------------------
+All floating-point numbers are handled as double (64 bits wide).
-GFX8 and GFX9 only.
+Floating-point numbers may be specified in hexadecimal and decimal formats:
-clamp
-~~~~~
+ ============== ======================================================== ========================================================
+ Format Syntax Note
+ ============== ======================================================== ========================================================
+ Decimal [-]?[0-9]*[.][0-9]*([eE][+-]?[0-9]*)? Must include either a decimal separator or an exponent.
+ Hexadecimal [-]0x[0-9a-fA-F]*(.[0-9a-fA-F]*)?[pP][+-]?[0-9a-fA-F]+
+ ============== ======================================================== ========================================================
-See a description :ref:`here<amdgpu_synid_clamp>`.
+Examples:
-omod
-~~~~
+.. code-block:: nasm
-See a description :ref:`here<amdgpu_synid_omod>`.
+ -1.234
+ 234e2
+ -0x1afp-10
+ 0x.1afp10
-GFX9 only.
+.. _amdgpu_synid_expression:
-.. _amdgpu_synid_dst_sel:
+Expressions
+===========
-dst_sel
-~~~~~~~
+An expression specifies an address or a numeric value.
+There are two kinds of expressions:
-Selects which bits in the destination are affected. By default, all bits are affected.
+* :ref:`Absolute<amdgpu_synid_absolute_expression>`.
+* :ref:`Relocatable<amdgpu_synid_relocatable_expression>`.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- dst_sel:DWORD Use bits 31:0.
- dst_sel:BYTE_0 Use bits 7:0.
- dst_sel:BYTE_1 Use bits 15:8.
- dst_sel:BYTE_2 Use bits 23:16.
- dst_sel:BYTE_3 Use bits 31:24.
- dst_sel:WORD_0 Use bits 15:0.
- dst_sel:WORD_1 Use bits 31:16.
- ======================================== ================================================
+.. _amdgpu_synid_absolute_expression:
+Absolute Expressions
+--------------------
-.. _amdgpu_synid_dst_unused:
+The value of an absolute expression remains the same after program relocation.
+Absolute expressions must not include unassigned and relocatable values
+such as labels.
-dst_unused
-~~~~~~~~~~
+Examples:
-Controls what to do with the bits in the destination which are not selected
-by :ref:`dst_sel<amdgpu_synid_dst_sel>`.
-By default, unused bits are preserved.
+.. code-block:: nasm
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- dst_unused:UNUSED_PAD Pad with zeros.
- dst_unused:UNUSED_SEXT Sign-extend upper bits, zero lower bits.
- dst_unused:UNUSED_PRESERVE Preserve bits.
- ======================================== ================================================
+ x = -1
+ y = x + 10
-.. _amdgpu_synid_src0_sel:
+.. _amdgpu_synid_relocatable_expression:
-src0_sel
-~~~~~~~~
+Relocatable Expressions
+-----------------------
-Controls which bits in the src0 are used. By default, all bits are used.
+The value of a relocatable expression depends on program relocation.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- src0_sel:DWORD Use bits 31:0.
- src0_sel:BYTE_0 Use bits 7:0.
- src0_sel:BYTE_1 Use bits 15:8.
- src0_sel:BYTE_2 Use bits 23:16.
- src0_sel:BYTE_3 Use bits 31:24.
- src0_sel:WORD_0 Use bits 15:0.
- src0_sel:WORD_1 Use bits 31:16.
- ======================================== ================================================
+Note that use of relocatable expressions is limited with branch targets
+and 32-bit :ref:`literals<amdgpu_synid_literal>`.
-.. _amdgpu_synid_src1_sel:
+Addition information about relocation may be found :ref:`here<amdgpu-relocation-records>`.
-src1_sel
-~~~~~~~~
+Examples:
-Controls which bits in the src1 are used. By default, all bits are used.
+.. code-block:: nasm
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- src1_sel:DWORD Use bits 31:0.
- src1_sel:BYTE_0 Use bits 7:0.
- src1_sel:BYTE_1 Use bits 15:8.
- src1_sel:BYTE_2 Use bits 23:16.
- src1_sel:BYTE_3 Use bits 31:24.
- src1_sel:WORD_0 Use bits 15:0.
- src1_sel:WORD_1 Use bits 31:16.
- ======================================== ================================================
+ y = x + 10 // x is not yet defined. Undefined symbols are assumed to be PC-relative.
+ z = .
-VOP1/VOP2/VOPC SDWA Operand Modifiers
--------------------------------------
+Expression Data Type
+--------------------
-Operand modifiers are not used separately. They are applied to source operands.
+Expressions and operands of expressions are interpreted as 64-bit integers.
-GFX8 and GFX9 only.
+Expressions may include 64-bit :ref:`floating-point numbers<amdgpu_synid_floating-point_number>` (double).
+However these operands are also handled as 64-bit integers
+using binary representation of specified floating-point numbers.
+No conversion from floating-point to integer is performed.
-abs
-~~~
+Examples:
-See a description :ref:`here<amdgpu_synid_abs>`.
+.. code-block:: nasm
-neg
-~~~
+ x = 0.1 // x is assigned an integer 4591870180066957722 which is a binary representation of 0.1.
+ y = x + x // y is a sum of two integer values; it is not equal to 0.2!
-See a description :ref:`here<amdgpu_synid_neg>`.
+Syntax
+------
-.. _amdgpu_synid_sext:
+Expressions are composed of
+:ref:`symbols<amdgpu_synid_symbol>`,
+:ref:`integer numbers<amdgpu_synid_integer_number>`,
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>`,
+:ref:`binary operators<amdgpu_synid_expression_bin_op>`,
+:ref:`unary operators<amdgpu_synid_expression_un_op>` and subexpressions.
-sext
-~~~~
+Expressions may also use "." which is a reference to the current PC (program counter).
-Sign-extends value of a (sub-dword) operand to fill all 32 bits.
-Has no effect for 32-bit operands.
+The syntax of expressions is shown below::
-Valid for integer operands only.
+ expr ::= expr binop expr | primaryexpr ;
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- sext(<operand>) Sign-extend operand value.
- ======================================== ================================================
+ primaryexpr ::= '(' expr ')' | symbol | number | '.' | unop primaryexpr ;
-VOP3 Modifiers
---------------
+ binop ::= '&&'
+ | '||'
+ | '|'
+ | '^'
+ | '&'
+ | '!'
+ | '=='
+ | '!='
+ | '<>'
+ | '<'
+ | '<='
+ | '>'
+ | '>='
+ | '<<'
+ | '>>'
+ | '+'
+ | '-'
+ | '*'
+ | '/'
+ | '%' ;
-.. _amdgpu_synid_vop3_op_sel:
+ unop ::= '~'
+ | '+'
+ | '-'
+ | '!' ;
-vop3_op_sel
-~~~~~~~~~~~
+.. _amdgpu_synid_expression_bin_op:
-Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
-By default, low bits are used for all operands.
+Binary Operators
+----------------
-The number of values specified with the op_sel modifier must match the number of instruction
-operands (both source and destination). First value controls src0, second value controls src1
-and so on, except that the last value controls destination.
-The value 0 selects the low bits, while 1 selects the high bits.
+Binary operators are described in the following table.
+They operate on and produce 64-bit integers.
+Operators with higher priority are performed first.
+
+ ========== ========= ===============================================
+ Operator Priority Meaning
+ ========== ========= ===============================================
+ \* 5 Integer multiplication.
+ / 5 Integer division.
+ % 5 Integer signed remainder.
+ \+ 4 Integer addition.
+ \- 4 Integer subtraction.
+ << 3 Integer shift left.
+ >> 3 Logical shift right.
+ == 2 Equality comparison.
+ != 2 Inequality comparison.
+ <> 2 Inequality comparison.
+ < 2 Signed less than comparison.
+ <= 2 Signed less than or equal comparison.
+ > 2 Signed greater than comparison.
+ >= 2 Signed greater than or equal comparison.
+ \| 1 Bitwise or.
+ ^ 1 Bitwise xor.
+ & 1 Bitwise and.
+ && 0 Logical and.
+ || 0 Logical or.
+ ========== ========= ===============================================
-Note. op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
-by op_sel must be 0.
+.. _amdgpu_synid_expression_un_op:
-GFX9 only.
+Unary Operators
+---------------
- ======================================== ============================================================
- Syntax Description
- ======================================== ============================================================
- op_sel:[{0..1},{0..1}] Select operand bits for instructions with 1 source operand.
- op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
- op_sel:[{0..1},{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
- ======================================== ============================================================
+Unary operators are described in the following table.
+They operate on and produce 64-bit integers.
-.. _amdgpu_synid_clamp:
+ ========== ===============================================
+ Operator Meaning
+ ========== ===============================================
+ ! Logical negation.
+ ~ Bitwise negation.
+ \+ Integer unary plus.
+ \- Integer unary minus.
+ ========== ===============================================
-clamp
-~~~~~
+.. _amdgpu_synid_symbol:
-Clamp meaning depends on instruction.
+Symbols
+-------
-For *v_cmp* instructions, clamp modifier indicates that the compare signals
-if a floating point exception occurs. By default, signaling is disabled.
-Not supported by GFX7.
+A symbol is a named 64-bit value, representing a relocatable
+address or an absolute (non-relocatable) number.
-For integer operations, clamp modifier indicates that the result must be clamped
-to the largest and smallest representable value. By default, there is no clamping.
-Integer clamping is not supported by GFX7.
+Symbol names have the following syntax:
+ ``[a-zA-Z_.][a-zA-Z0-9_$.@]*``
-For floating point operations, clamp modifier indicates that the result must be clamped
-to the range [0.0, 1.0]. By default, there is no clamping.
+The table below provides several examples of syntax used for symbol definition.
-Note. Clamp modifier is applied after :ref:`output modifiers<amdgpu_synid_omod>` (if any).
+ ================ ==========================================================
+ Syntax Meaning
+ ================ ==========================================================
+ .globl <S> Declares a global symbol S without assigning it a value.
+ .set <S>, <E> Assigns the value of an expression E to a symbol S.
+ <S> = <E> Assigns the value of an expression E to a symbol S.
+ <S>: Declares a label S and assigns it the current PC value.
+ ================ ==========================================================
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- clamp Enables clamping (or signaling).
- ======================================== ================================================
+A symbol may be used before it is declared or assigned;
+unassigned symbols are assumed to be PC-relative.
-.. _amdgpu_synid_omod:
+Addition information about symbols may be found :ref:`here<amdgpu-symbols>`.
-omod
-~~~~
+.. _amdgpu_synid_conv:
-Specifies if an output modifier must be applied to the result.
-By default, no output modifiers are applied.
+Conversions
+===========
-Note. Output modifiers are applied before :ref:`clamping<amdgpu_synid_clamp>` (if any).
+This section describes what happens when a 64-bit
+:ref:`integer number<amdgpu_synid_integer_number>`, a
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>` or a
+:ref:`symbol<amdgpu_synid_symbol>`
+is used for an operand which has a different type or size.
-Output modifiers are valid for f32 and f64 floating point results only.
-They must not be used with f16.
+Depending on operand kind, this conversion is performed by either assembler or AMDGPU H/W:
-Note. *v_cvt_f16_f32* is an exception. This instruction produces f16 result
-but accepts output modifiers.
+* Values encoded as :ref:`inline constants<amdgpu_synid_constant>` are handled by H/W.
+* Values encoded as :ref:`literals<amdgpu_synid_literal>` are converted by assembler.
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- mul:2 Multiply the result by 2.
- mul:4 Multiply the result by 4.
- div:2 Multiply the result by 0.5.
- ======================================== ================================================
+.. _amdgpu_synid_const_conv:
-VOP3 Operand Modifiers
-----------------------
+Inline Constants
+----------------
-Operand modifiers are not used separately. They are applied to source operands.
+.. _amdgpu_synid_int_const_conv:
-.. _amdgpu_synid_abs:
+Integer Inline Constants
+~~~~~~~~~~~~~~~~~~~~~~~~
-abs
-~~~
+Integer :ref:`inline constants<amdgpu_synid_constant>`
+may be thought of as 64-bit
+:ref:`integer numbers<amdgpu_synid_integer_number>`;
+when used as operands they are truncated to the size of
+:ref:`expected operand type<amdgpu_syn_instruction_type>`.
+No data type conversions are performed.
-Computes absolute value of its operand. Applied before :ref:`neg<amdgpu_synid_neg>` (if any).
-Valid for floating point operands only.
+Examples:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- abs(<operand>) Get absolute value of operand.
- \|<operand>| The same as above.
- ======================================== ================================================
+.. code-block:: nasm
-.. _amdgpu_synid_neg:
+ // GFX9
-neg
-~~~
+ v_add_u16 v0, -1, 0 // v0 = 0xFFFF
+ v_add_f16 v0, -1, 0 // v0 = 0xFFFF (NaN)
-Computes negative value of its operand. Applied after :ref:`abs<amdgpu_synid_abs>` (if any).
-Valid for floating point operands only.
+ v_add_u32 v0, -1, 0 // v0 = 0xFFFFFFFF
+ v_add_f32 v0, -1, 0 // v0 = 0xFFFFFFFF (NaN)
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- neg(<operand>) Get negative value of operand.
- -<operand> The same as above.
- ======================================== ================================================
+.. _amdgpu_synid_fp_const_conv:
-VOP3P Modifiers
----------------
+Floating-Point Inline Constants
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-This section describes modifiers of regular VOP3P instructions.
-*v_mad_mix* modifiers are described :ref:`in a separate section<amdgpu_synid_mad_mix>`.
+Floating-point :ref:`inline constants<amdgpu_synid_constant>`
+may be thought of as 64-bit
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>`;
+when used as operands they are converted to a floating-point number of
+:ref:`expected operand size<amdgpu_syn_instruction_type>`.
-GFX9 only.
+Examples:
-.. _amdgpu_synid_op_sel:
+.. code-block:: nasm
-op_sel
-~~~~~~
+ // GFX9
-Selects the low [15:0] or high [31:16] operand bits as input to the operation
-which results in the lower-half of the destination.
-By default, low bits are used for all operands.
+ v_add_f16 v0, 1.0, 0 // v0 = 0x3C00 (1.0)
+ v_add_u16 v0, 1.0, 0 // v0 = 0x3C00
-The number of values specified with the op_sel modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
-The value 0 selects the low bits, while 1 selects the high bits.
+ v_add_f32 v0, 1.0, 0 // v0 = 0x3F800000 (1.0)
+ v_add_u32 v0, 1.0, 0 // v0 = 0x3F800000
- ======================================== =============================================================
- Syntax Description
- ======================================== =============================================================
- op_sel:[{0..1}] Select operand bits for instructions with 1 source operand.
- op_sel:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
- op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
- ======================================== =============================================================
-.. _amdgpu_synid_op_sel_hi:
+.. _amdgpu_synid_lit_conv:
-op_sel_hi
-~~~~~~~~~
+Literals
+--------
-Selects the low [15:0] or high [31:16] operand bits as input to the operation
-which results in the upper-half of the destination.
-By default, high bits are used for all operands.
+.. _amdgpu_synid_int_lit_conv:
-The number of values specified with the op_sel_hi modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
-The value 0 selects the low bits, while 1 selects the high bits.
+Integer Literals
+~~~~~~~~~~~~~~~~
- ======================================== =============================================================
- Syntax Description
- ======================================== =============================================================
- op_sel_hi:[{0..1}] Select operand bits for instructions with 1 source operand.
- op_sel_hi:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
- op_sel_hi:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
- ======================================== =============================================================
+Integer :ref:`literals<amdgpu_synid_literal>`
+are specified as 64-bit :ref:`integer numbers<amdgpu_synid_integer_number>`.
-.. _amdgpu_synid_neg_lo:
+When used as operands they are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>` as described below.
-neg_lo
-~~~~~~
+ ============== ============== =============== ====================================================================
+ Expected type Condition Result Note
+ ============== ============== =============== ====================================================================
+ i16, u16, b16 cond(num, 16) num.u16 Truncate to 16 bits.
+ i32, u32, b32 cond(num, 32) num.u32 Truncate to 32 bits.
+ i64 cond(num, 32) {-1, num.i32} Truncate to 32 bits and then sign-extend the result to 64 bits.
+ u64, b64 cond(num, 32) { 0, num.u32} Truncate to 32 bits and then zero-extend the result to 64 bits.
+ f16 cond(num, 16) num.u16 Use low 16 bits as an f16 value.
+ f32 cond(num, 32) num.u32 Use low 32 bits as an f32 value.
+ f64 cond(num, 32) {num.u32, 0} Use low 32 bits of the number as high 32 bits
+ of the result; low 32 bits of the result are zeroed.
+ ============== ============== =============== ====================================================================
-Specifies whether to change sign of operand values selected by
-:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used
-as input to the operation which results in the upper-half of the destination.
+The condition *cond(X,S)* indicates if a 64-bit number *X*
+can be converted to a smaller size *S* by truncation of upper bits.
+There are two cases when the conversion is possible:
-The number of values specified with this modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
+* The truncated bits are all 0.
+* The truncated bits are all 1 and the value after truncation has its MSB bit set.
-The value 0 indicates that the corresponding operand value is used unmodified,
-the value 1 indicates that negative value of the operand must be used.
+Examples of valid literals:
-By default, operand values are used unmodified.
+.. code-block:: nasm
-This modifier is valid for floating point operands only.
+ // GFX9
- ======================================== ==================================================================
- Syntax Description
- ======================================== ==================================================================
- neg_lo:[{0..1}] Select affected operands for instructions with 1 source operand.
- neg_lo:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
- neg_lo:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
- ======================================== ==================================================================
+ v_add_u16 v0, 0xff00, v0 // value after conversion: 0xff00
+ v_add_u16 v0, 0xffffffffffffff00, v0 // value after conversion: 0xff00
+ v_add_u16 v0, -256, v0 // value after conversion: 0xff00
-.. _amdgpu_synid_neg_hi:
+ s_bfe_i64 s[0:1], 0xffefffff, s3 // value after conversion: 0xffffffffffefffff
+ s_bfe_u64 s[0:1], 0xffefffff, s3 // value after conversion: 0x00000000ffefffff
+ v_ceil_f64_e32 v[0:1], 0xffefffff // value after conversion: 0xffefffff00000000 (-1.7976922776554302e308)
-neg_hi
-~~~~~~
+Examples of invalid literals:
-Specifies whether to change sign of operand values selected by
-:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used
-as input to the operation which results in the upper-half of the destination.
+.. code-block:: nasm
-The number of values specified with this modifier must match the number of source
-operands. First value controls src0, second value controls src1 and so on.
+ // GFX9
-The value 0 indicates that the corresponding operand value is used unmodified,
-the value 1 indicates that negative value of the operand must be used.
+ v_add_u16 v0, 0x1ff00, v0 // conversion is not possible as truncated bits are not all 0 or 1
+ v_add_u16 v0, 0xffffffffffff00ff, v0 // conversion is not possible as truncated bits do not match MSB of the result
-By default, operand values are used unmodified.
+.. _amdgpu_synid_fp_lit_conv:
-This modifier is valid for floating point operands only.
+Floating-Point Literals
+~~~~~~~~~~~~~~~~~~~~~~~
- ======================================== ==================================================================
- Syntax Description
- ======================================== ==================================================================
- neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand.
- neg_hi:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
- neg_hi:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
- ======================================== ==================================================================
+Floating-point :ref:`literals<amdgpu_synid_literal>` are specified as 64-bit
+:ref:`floating-point numbers<amdgpu_synid_floating-point_number>`.
-clamp
-~~~~~
+When used as operands they are converted to
+:ref:`expected operand type<amdgpu_syn_instruction_type>` as described below.
-See a description :ref:`here<amdgpu_synid_clamp>`.
+ ============== ============== ================= =================================================================
+ Expected type Condition Result Note
+ ============== ============== ================= =================================================================
+ i16, u16, b16 cond(num, 16) f16(num) Convert to f16 and use bits of the result as an integer value.
+ i32, u32, b32 cond(num, 32) f32(num) Convert to f32 and use bits of the result as an integer value.
+ i64, u64, b64 false \- Conversion disabled because of an unclear semantics.
+ f16 cond(num, 16) f16(num) Convert to f16.
+ f32 cond(num, 32) f32(num) Convert to f32.
+ f64 true {num.u32.hi, 0} Use high 32 bits of the number as high 32 bits of the result;
+ zero-fill low 32 bits of the result.
-.. _amdgpu_synid_mad_mix:
+ Note that the result may differ from the original number.
+ ============== ============== ================= =================================================================
-VOP3P V_MAD_MIX Modifiers
--------------------------
+The condition *cond(X,S)* indicates if an f64 number *X* can be converted
+to a smaller *S*-bit floating-point type without overflow or underflow.
+Precision lost is allowed.
-These instructions use VOP3P format but have different modifiers.
+Examples of valid literals:
-GFX9 only.
+.. code-block:: nasm
-.. _amdgpu_synid_mad_mix_op_sel:
+ // GFX9
-mad_mix_op_sel
-~~~~~~~~~~~~~~
+ v_add_f16 v1, 65500.0, v2
+ v_add_f32 v1, 65600.0, v2
-This operand has meaning only for 16-bit source operands as indicated by
-:ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
-It specifies to select either the low [15:0] or high [31:16] operand bits
-as input to the operation.
+ // value before conversion: 0x7fefffffffffffff (1.7976931348623157e308)
+ v_ceil_f64 v[0:1], 1.7976931348623157e308 // value after conversion: 0x7fefffff00000000 (1.7976922776554302e308)
-The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
-By default, low bits are used for all operands.
+Examples of invalid literals:
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- op_sel:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand.
- ======================================== ================================================
+.. code-block:: nasm
-.. _amdgpu_synid_mad_mix_op_sel_hi:
+ // GFX9
-mad_mix_op_sel_hi
-~~~~~~~~~~~~~~~~~
+ v_add_f16 v1, 65600.0, v2 // cannot be converted to f16 because of overflow
-Selects the size of source operands: either 32 bits or 16 bits.
-By default, 32 bits are used for all source operands.
+.. _amdgpu_synid_exp_conv:
-The value 0 indicates 32 bits, the value 1 indicates 16 bits.
-The location of 16 bits in the operand may be specified by
-:ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+Expressions
+~~~~~~~~~~~
- ======================================== ================================================
- Syntax Description
- ======================================== ================================================
- op_sel_hi:[{0..1},{0..1},{0..1}] Select size of each source operand.
- ======================================== ================================================
+Expressions operate with and result in 64-bit integers.
-abs
-~~~
+When used as operands they are truncated to
+:ref:`expected operand size<amdgpu_syn_instruction_type>`.
+No data type conversions are performed.
-See a description :ref:`here<amdgpu_synid_abs>`.
+Examples:
-neg
-~~~
+.. code-block:: nasm
-See a description :ref:`here<amdgpu_synid_neg>`.
+ // GFX9
-clamp
-~~~~~
+ x = 0.1
+ v_sqrt_f32 v0, x // v0 = [low 32 bits of 0.1 (double)]
+ v_sqrt_f32 v0, (0.1 + 0) // the same as above
+ v_sqrt_f32 v0, 0.1 // v0 = [0.1 (double) converted to float]
-See a description :ref:`here<amdgpu_synid_clamp>`.
Modified: llvm/trunk/docs/AMDGPUUsage.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUUsage.rst?rev=349368&r1=349367&r2=349368&view=diff
==============================================================================
--- llvm/trunk/docs/AMDGPUUsage.rst (original)
+++ llvm/trunk/docs/AMDGPUUsage.rst Mon Dec 17 09:38:11 2018
@@ -4558,21 +4558,26 @@ Instructions
.. toctree::
:hidden:
- AMDGPUAsmGFX7
- AMDGPUAsmGFX8
- AMDGPUAsmGFX9
+ AMDGPU/AMDGPUAsmGFX7
+ AMDGPU/AMDGPUAsmGFX8
+ AMDGPU/AMDGPUAsmGFX9
+ AMDGPUModifierSyntax
AMDGPUOperandSyntax
+ AMDGPUInstructionSyntax
+ AMDGPUInstructionNotation
-An instruction has the following syntax:
+An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:
- *<opcode> <operand0>, <operand1>,... <modifier0> <modifier1>...*
+ ``<``\ *opcode*\ ``> <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,... <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
-Note that operands are normally comma-separated while modifiers are space-separated.
+:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while
+:doc:`modifiers<AMDGPUModifierSyntax>` are space-separated.
-The order of operands and modifiers is fixed. Most modifiers are optional and may be omitted.
+The order of *operands* and *modifiers* is fixed.
+Most *modifiers* are optional and may be omitted.
-See detailed instruction syntax description for :doc:`GFX7<AMDGPUAsmGFX7>`,
-:doc:`GFX8<AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPUAsmGFX9>`.
+See detailed instruction syntax description for :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`,
+:doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`.
Note that features under development are not included in this description.
@@ -4583,22 +4588,12 @@ operands, refer to one of instruction se
Operands
~~~~~~~~
-The following syntax for register operands is supported:
-
-* SGPR registers: s0, ... or s[0], ...
-* VGPR registers: v0, ... or v[0], ...
-* TTMP registers: ttmp0, ... or ttmp[0], ...
-* Special registers: exec (exec_lo, exec_hi), vcc (vcc_lo, vcc_hi), flat_scratch (flat_scratch_lo, flat_scratch_hi)
-* Special trap registers: tba (tba_lo, tba_hi), tma (tma_lo, tma_hi)
-* Register pairs, quads, etc: s[2:3], v[10:11], ttmp[5:6], s[4:7], v[12:15], ttmp[4:7], s[8:15], ...
-* Register lists: [s0, s1], [ttmp0, ttmp1, ttmp2, ttmp3]
-* Register index expressions: v[2*2], s[1-1:2-1]
-* 'off' indicates that an operand is not enabled
+Detailed description of operands may be found :doc:`here<AMDGPUOperandSyntax>`.
Modifiers
~~~~~~~~~
-Detailed description of modifiers may be found :doc:`here<AMDGPUOperandSyntax>`.
+Detailed description of modifiers may be found :doc:`here<AMDGPUModifierSyntax>`.
Instruction Examples
~~~~~~~~~~~~~~~~~~~~
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