[PATCH] D55759: AMDGPU/GlobalISel: Introduce vcc reg bank

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellar.
Herald added subscribers: t-tye, tpr, dstuttard, kristof.beyls, rovka, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

I'm not entirely sure this is the correct thing
to do with the global isel philosophy, but I think
this is necessary to handle how differently SGPRs
are used normally vs. from a condition.

      

For example, it makes sense to allow a copy
from a VGPR to an SGPR, but it makes no sense
to allow a copy from VGPRs to SGPRs used as
select mask.

      

This avoids regbankselecting strange code with
a truncate feeding directly into a condition field.
Now a copy is forced from sgpr(s1) to vcc, which is
more sensible to handle.

      

Some of these issues could probably avoided with making enough
operations resulting in i1 illegal. I think we can't avoid
this register bank for legality.

      

For example, an i1 and implemented with s_and_b64 for
vector conditions is legal. An i1 and for scalar conditions
is illegal and can't be done with just one scc.


https://reviews.llvm.org/D55759

Files:
  lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  lib/Target/AMDGPU/AMDGPURegisterBanks.td
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-saddo.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssubo.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir

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