[llvm] r349270 - Regenerate neon copy tests. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 15 06:23:19 PST 2018
Author: rksimon
Date: Sat Dec 15 06:23:18 2018
New Revision: 349270
URL: http://llvm.org/viewvc/llvm-project?rev=349270&view=rev
Log:
Regenerate neon copy tests. NFCI.
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll?rev=349270&r1=349269&r2=349270&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll Sat Dec 15 06:23:18 2018
@@ -1,58 +1,81 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
-
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
; CHECK-LABEL: ins16bw:
-; CHECK: mov {{v[0-9]+}}.b[15], {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.b[15], w0
+; CHECK-NEXT: ret
%tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
ret <16 x i8> %tmp3
}
define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
; CHECK-LABEL: ins8hw:
-; CHECK: mov {{v[0-9]+}}.h[6], {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.h[6], w0
+; CHECK-NEXT: ret
%tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
ret <8 x i16> %tmp3
}
define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
; CHECK-LABEL: ins4sw:
-; CHECK: mov {{v[0-9]+}}.s[2], {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.s[2], w0
+; CHECK-NEXT: ret
%tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
ret <4 x i32> %tmp3
}
define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
; CHECK-LABEL: ins2dw:
-; CHECK: mov {{v[0-9]+}}.d[1], {{x[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.d[1], x0
+; CHECK-NEXT: ret
%tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
ret <2 x i64> %tmp3
}
define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
; CHECK-LABEL: ins8bw:
-; CHECK: mov {{v[0-9]+}}.b[5], {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.b[5], w0
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
ret <8 x i8> %tmp3
}
define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
; CHECK-LABEL: ins4hw:
-; CHECK: mov {{v[0-9]+}}.h[3], {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.h[3], w0
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
ret <4 x i16> %tmp3
}
define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
; CHECK-LABEL: ins2sw:
-; CHECK: mov {{v[0-9]+}}.s[1], {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.s[1], w0
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
ret <2 x i32> %tmp3
}
define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
; CHECK-LABEL: ins16b16:
-; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v1.b[15], v0.b[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <16 x i8> %tmp1, i32 2
%tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
ret <16 x i8> %tmp4
@@ -60,7 +83,10 @@ define <16 x i8> @ins16b16(<16 x i8> %tm
define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
; CHECK-LABEL: ins8h8:
-; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v1.h[7], v0.h[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
ret <8 x i16> %tmp4
@@ -68,7 +94,10 @@ define <8 x i16> @ins8h8(<8 x i16> %tmp1
define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
; CHECK-LABEL: ins4s4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v1.s[1], v0.s[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
ret <4 x i32> %tmp4
@@ -76,7 +105,10 @@ define <4 x i32> @ins4s4(<4 x i32> %tmp1
define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
; CHECK-LABEL: ins2d2:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x i64> %tmp1, i32 0
%tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
ret <2 x i64> %tmp4
@@ -84,7 +116,10 @@ define <2 x i64> @ins2d2(<2 x i64> %tmp1
define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
; CHECK-LABEL: ins4f4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v1.s[1], v0.s[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x float> %tmp1, i32 2
%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
ret <4 x float> %tmp4
@@ -92,7 +127,10 @@ define <4 x float> @ins4f4(<4 x float> %
define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
; CHECK-LABEL: ins2df2:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x double> %tmp1, i32 0
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
ret <2 x double> %tmp4
@@ -100,7 +138,11 @@ define <2 x double> @ins2df2(<2 x double
define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
; CHECK-LABEL: ins8b16:
-; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.b[15], v0.b[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i8> %tmp1, i32 2
%tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
ret <16 x i8> %tmp4
@@ -108,7 +150,11 @@ define <16 x i8> @ins8b16(<8 x i8> %tmp1
define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
; CHECK-LABEL: ins4h8:
-; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.h[7], v0.h[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
ret <8 x i16> %tmp4
@@ -116,7 +162,11 @@ define <8 x i16> @ins4h8(<4 x i16> %tmp1
define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
; CHECK-LABEL: ins2s4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.s[1], v0.s[1]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x i32> %tmp1, i32 1
%tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
ret <4 x i32> %tmp4
@@ -124,7 +174,11 @@ define <4 x i32> @ins2s4(<2 x i32> %tmp1
define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
; CHECK-LABEL: ins1d2:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <1 x i64> %tmp1, i32 0
%tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
ret <2 x i64> %tmp4
@@ -132,7 +186,11 @@ define <2 x i64> @ins1d2(<1 x i64> %tmp1
define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
; CHECK-LABEL: ins2f4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.s[1], v0.s[1]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x float> %tmp1, i32 1
%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
ret <4 x float> %tmp4
@@ -140,7 +198,10 @@ define <4 x float> @ins2f4(<2 x float> %
define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
; CHECK-LABEL: ins1f2:
-; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
%tmp3 = extractelement <1 x double> %tmp1, i32 0
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
ret <2 x double> %tmp4
@@ -148,7 +209,11 @@ define <2 x double> @ins1f2(<1 x double>
define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
; CHECK-LABEL: ins16b8:
-; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v1.b[7], v0.b[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <16 x i8> %tmp1, i32 2
%tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
ret <8 x i8> %tmp4
@@ -156,7 +221,11 @@ define <8 x i8> @ins16b8(<16 x i8> %tmp1
define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
; CHECK-LABEL: ins8h4:
-; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v1.h[3], v0.h[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
ret <4 x i16> %tmp4
@@ -164,7 +233,11 @@ define <4 x i16> @ins8h4(<8 x i16> %tmp1
define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
; CHECK-LABEL: ins4s2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v1.s[1], v0.s[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
ret <2 x i32> %tmp4
@@ -172,7 +245,11 @@ define <2 x i32> @ins4s2(<4 x i32> %tmp1
define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
; CHECK-LABEL: ins2d1:
-; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v1.d[0], v0.d[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x i64> %tmp1, i32 0
%tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
ret <1 x i64> %tmp4
@@ -180,7 +257,11 @@ define <1 x i64> @ins2d1(<2 x i64> %tmp1
define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
; CHECK-LABEL: ins4f2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v1.s[1], v0.s[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x float> %tmp1, i32 2
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
ret <2 x float> %tmp4
@@ -188,7 +269,10 @@ define <2 x float> @ins4f2(<4 x float> %
define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
; CHECK-LABEL: ins2f1:
-; CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.2d, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x double> %tmp1, i32 1
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
ret <1 x double> %tmp4
@@ -196,7 +280,12 @@ define <1 x double> @ins2f1(<2 x double>
define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
; CHECK-LABEL: ins8b8:
-; CHECK: mov {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.b[4], v0.b[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i8> %tmp1, i32 2
%tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
ret <8 x i8> %tmp4
@@ -204,7 +293,12 @@ define <8 x i8> @ins8b8(<8 x i8> %tmp1,
define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
; CHECK-LABEL: ins4h4:
-; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.h[3], v0.h[2]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
ret <4 x i16> %tmp4
@@ -212,7 +306,12 @@ define <4 x i16> @ins4h4(<4 x i16> %tmp1
define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
; CHECK-LABEL: ins2s2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.s[1], v0.s[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x i32> %tmp1, i32 0
%tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
ret <2 x i32> %tmp4
@@ -220,7 +319,12 @@ define <2 x i32> @ins2s2(<2 x i32> %tmp1
define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
; CHECK-LABEL: ins1d1:
-; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.d[0], v0.d[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <1 x i64> %tmp1, i32 0
%tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
ret <1 x i64> %tmp4
@@ -228,7 +332,12 @@ define <1 x i64> @ins1d1(<1 x i64> %tmp1
define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
; CHECK-LABEL: ins2f2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.s[1], v0.s[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x float> %tmp1, i32 0
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
ret <2 x float> %tmp4
@@ -236,7 +345,8 @@ define <2 x float> @ins2f2(<2 x float> %
define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
; CHECK-LABEL: ins1df1:
-; CHECK-NOT: mov {{v[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
%tmp3 = extractelement <1 x double> %tmp1, i32 0
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
ret <1 x double> %tmp4
@@ -244,7 +354,9 @@ define <1 x double> @ins1df1(<1 x double
define i32 @umovw16b(<16 x i8> %tmp1) {
; CHECK-LABEL: umovw16b:
-; CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
+; CHECK: // %bb.0:
+; CHECK-NEXT: umov w0, v0.b[8]
+; CHECK-NEXT: ret
%tmp3 = extractelement <16 x i8> %tmp1, i32 8
%tmp4 = zext i8 %tmp3 to i32
ret i32 %tmp4
@@ -252,7 +364,9 @@ define i32 @umovw16b(<16 x i8> %tmp1) {
define i32 @umovw8h(<8 x i16> %tmp1) {
; CHECK-LABEL: umovw8h:
-; CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: umov w0, v0.h[2]
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = zext i16 %tmp3 to i32
ret i32 %tmp4
@@ -260,21 +374,28 @@ define i32 @umovw8h(<8 x i16> %tmp1) {
define i32 @umovw4s(<4 x i32> %tmp1) {
; CHECK-LABEL: umovw4s:
-; CHECK: mov {{w[0-9]+}}, {{v[0-9]+}}.s[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w0, v0.s[2]
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
ret i32 %tmp3
}
define i64 @umovx2d(<2 x i64> %tmp1) {
; CHECK-LABEL: umovx2d:
-; CHECK: mov {{x[0-9]+}}, {{v[0-9]+}}.d[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x0, v0.d[1]
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x i64> %tmp1, i32 1
ret i64 %tmp3
}
define i32 @umovw8b(<8 x i8> %tmp1) {
; CHECK-LABEL: umovw8b:
-; CHECK: mov {{w[0-9]+}}, {{v[0-9]+}}.b[7]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: umov w0, v0.b[7]
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i8> %tmp1, i32 7
%tmp4 = zext i8 %tmp3 to i32
ret i32 %tmp4
@@ -282,7 +403,10 @@ define i32 @umovw8b(<8 x i8> %tmp1) {
define i32 @umovw4h(<4 x i16> %tmp1) {
; CHECK-LABEL: umovw4h:
-; CHECK: mov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: umov w0, v0.h[2]
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = zext i16 %tmp3 to i32
ret i32 %tmp4
@@ -290,21 +414,30 @@ define i32 @umovw4h(<4 x i16> %tmp1) {
define i32 @umovw2s(<2 x i32> %tmp1) {
; CHECK-LABEL: umovw2s:
-; CHECK: mov {{w[0-9]+}}, {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov w0, v0.s[1]
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x i32> %tmp1, i32 1
ret i32 %tmp3
}
define i64 @umovx1d(<1 x i64> %tmp1) {
; CHECK-LABEL: umovx1d:
-; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%tmp3 = extractelement <1 x i64> %tmp1, i32 0
ret i64 %tmp3
}
define i32 @smovw16b(<16 x i8> %tmp1) {
; CHECK-LABEL: smovw16b:
-; CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
+; CHECK: // %bb.0:
+; CHECK-NEXT: smov w8, v0.b[8]
+; CHECK-NEXT: add w0, w8, w8
+; CHECK-NEXT: ret
%tmp3 = extractelement <16 x i8> %tmp1, i32 8
%tmp4 = sext i8 %tmp3 to i32
%tmp5 = add i32 %tmp4, %tmp4
@@ -313,7 +446,10 @@ define i32 @smovw16b(<16 x i8> %tmp1) {
define i32 @smovw8h(<8 x i16> %tmp1) {
; CHECK-LABEL: smovw8h:
-; CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: smov w8, v0.h[2]
+; CHECK-NEXT: add w0, w8, w8
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i32
%tmp5 = add i32 %tmp4, %tmp4
@@ -322,7 +458,9 @@ define i32 @smovw8h(<8 x i16> %tmp1) {
define i64 @smovx16b(<16 x i8> %tmp1) {
; CHECK-LABEL: smovx16b:
-; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[8]
+; CHECK: // %bb.0:
+; CHECK-NEXT: smov x0, v0.b[8]
+; CHECK-NEXT: ret
%tmp3 = extractelement <16 x i8> %tmp1, i32 8
%tmp4 = sext i8 %tmp3 to i64
ret i64 %tmp4
@@ -330,7 +468,9 @@ define i64 @smovx16b(<16 x i8> %tmp1) {
define i64 @smovx8h(<8 x i16> %tmp1) {
; CHECK-LABEL: smovx8h:
-; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: smov x0, v0.h[2]
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i64
ret i64 %tmp4
@@ -338,7 +478,9 @@ define i64 @smovx8h(<8 x i16> %tmp1) {
define i64 @smovx4s(<4 x i32> %tmp1) {
; CHECK-LABEL: smovx4s:
-; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: smov x0, v0.s[2]
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = sext i32 %tmp3 to i64
ret i64 %tmp4
@@ -346,7 +488,11 @@ define i64 @smovx4s(<4 x i32> %tmp1) {
define i32 @smovw8b(<8 x i8> %tmp1) {
; CHECK-LABEL: smovw8b:
-; CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[4]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: smov w8, v0.b[4]
+; CHECK-NEXT: add w0, w8, w8
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i8> %tmp1, i32 4
%tmp4 = sext i8 %tmp3 to i32
%tmp5 = add i32 %tmp4, %tmp4
@@ -355,7 +501,11 @@ define i32 @smovw8b(<8 x i8> %tmp1) {
define i32 @smovw4h(<4 x i16> %tmp1) {
; CHECK-LABEL: smovw4h:
-; CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: smov w8, v0.h[2]
+; CHECK-NEXT: add w0, w8, w8
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i32
%tmp5 = add i32 %tmp4, %tmp4
@@ -364,7 +514,10 @@ define i32 @smovw4h(<4 x i16> %tmp1) {
define i32 @smovx8b(<8 x i8> %tmp1) {
; CHECK-LABEL: smovx8b:
-; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.b[6]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: smov w0, v0.b[6]
+; CHECK-NEXT: ret
%tmp3 = extractelement <8 x i8> %tmp1, i32 6
%tmp4 = sext i8 %tmp3 to i32
ret i32 %tmp4
@@ -372,7 +525,10 @@ define i32 @smovx8b(<8 x i8> %tmp1) {
define i32 @smovx4h(<4 x i16> %tmp1) {
; CHECK-LABEL: smovx4h:
-; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: smov w0, v0.h[2]
+; CHECK-NEXT: ret
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i32
ret i32 %tmp4
@@ -380,7 +536,10 @@ define i32 @smovx4h(<4 x i16> %tmp1) {
define i64 @smovx2s(<2 x i32> %tmp1) {
; CHECK-LABEL: smovx2s:
-; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: smov x0, v0.s[1]
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x i32> %tmp1, i32 1
%tmp4 = sext i32 %tmp3 to i64
ret i64 %tmp4
@@ -388,35 +547,52 @@ define i64 @smovx2s(<2 x i32> %tmp1) {
define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {
; CHECK-LABEL: test_vcopy_lane_s8:
-; CHECK: mov {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.b[5], v1.b[3]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>
ret <8 x i8> %vset_lane
}
define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {
; CHECK-LABEL: test_vcopyq_laneq_s8:
-; CHECK: mov {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.b[14], v1.b[6]
+; CHECK-NEXT: ret
%vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15>
ret <16 x i8> %vset_lane
}
define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {
; CHECK-LABEL: test_vcopy_lane_swap_s8:
-; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.b[7], v0.b[0]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
ret <8 x i8> %vset_lane
}
define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
; CHECK-LABEL: test_vcopyq_laneq_swap_s8:
-; CHECK: mov {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v1.b[0], v0.b[15]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <16 x i8> %vset_lane
}
define <8 x i8> @test_vdup_n_u8(i8 %v1) #0 {
; CHECK-LABEL: test_vdup_n_u8:
-; CHECK: dup {{v[0-9]+}}.8b, {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.8b, w0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <8 x i8> undef, i8 %v1, i32 0
%vecinit1.i = insertelement <8 x i8> %vecinit.i, i8 %v1, i32 1
%vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 %v1, i32 2
@@ -430,7 +606,9 @@ define <8 x i8> @test_vdup_n_u8(i8 %v1)
define <4 x i16> @test_vdup_n_u16(i16 %v1) #0 {
; CHECK-LABEL: test_vdup_n_u16:
-; CHECK: dup {{v[0-9]+}}.4h, {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.4h, w0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <4 x i16> undef, i16 %v1, i32 0
%vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %v1, i32 1
%vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %v1, i32 2
@@ -440,7 +618,9 @@ define <4 x i16> @test_vdup_n_u16(i16 %v
define <2 x i32> @test_vdup_n_u32(i32 %v1) #0 {
; CHECK-LABEL: test_vdup_n_u32:
-; CHECK: dup {{v[0-9]+}}.2s, {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.2s, w0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <2 x i32> undef, i32 %v1, i32 0
%vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %v1, i32 1
ret <2 x i32> %vecinit1.i
@@ -448,14 +628,18 @@ define <2 x i32> @test_vdup_n_u32(i32 %v
define <1 x i64> @test_vdup_n_u64(i64 %v1) #0 {
; CHECK-LABEL: test_vdup_n_u64:
-; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <1 x i64> undef, i64 %v1, i32 0
ret <1 x i64> %vecinit.i
}
define <16 x i8> @test_vdupq_n_u8(i8 %v1) #0 {
; CHECK-LABEL: test_vdupq_n_u8:
-; CHECK: dup {{v[0-9]+}}.16b, {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.16b, w0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <16 x i8> undef, i8 %v1, i32 0
%vecinit1.i = insertelement <16 x i8> %vecinit.i, i8 %v1, i32 1
%vecinit2.i = insertelement <16 x i8> %vecinit1.i, i8 %v1, i32 2
@@ -477,7 +661,9 @@ define <16 x i8> @test_vdupq_n_u8(i8 %v1
define <8 x i16> @test_vdupq_n_u16(i16 %v1) #0 {
; CHECK-LABEL: test_vdupq_n_u16:
-; CHECK: dup {{v[0-9]+}}.8h, {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.8h, w0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <8 x i16> undef, i16 %v1, i32 0
%vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %v1, i32 1
%vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %v1, i32 2
@@ -491,7 +677,9 @@ define <8 x i16> @test_vdupq_n_u16(i16 %
define <4 x i32> @test_vdupq_n_u32(i32 %v1) #0 {
; CHECK-LABEL: test_vdupq_n_u32:
-; CHECK: dup {{v[0-9]+}}.4s, {{w[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.4s, w0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <4 x i32> undef, i32 %v1, i32 0
%vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %v1, i32 1
%vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %v1, i32 2
@@ -501,7 +689,9 @@ define <4 x i32> @test_vdupq_n_u32(i32 %
define <2 x i64> @test_vdupq_n_u64(i64 %v1) #0 {
; CHECK-LABEL: test_vdupq_n_u64:
-; CHECK: dup {{v[0-9]+}}.2d, {{x[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.2d, x0
+; CHECK-NEXT: ret
%vecinit.i = insertelement <2 x i64> undef, i64 %v1, i32 0
%vecinit1.i = insertelement <2 x i64> %vecinit.i, i64 %v1, i32 1
ret <2 x i64> %vecinit1.i
@@ -509,190 +699,252 @@ define <2 x i64> @test_vdupq_n_u64(i64 %
define <8 x i8> @test_vdup_lane_s8(<8 x i8> %v1) #0 {
; CHECK-LABEL: test_vdup_lane_s8:
-; CHECK: dup {{v[0-9]+}}.8b, {{v[0-9]+}}.b[5]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.8b, v0.b[5]
+; CHECK-NEXT: ret
%shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <8 x i8> %shuffle
}
define <4 x i16> @test_vdup_lane_s16(<4 x i16> %v1) #0 {
; CHECK-LABEL: test_vdup_lane_s16:
-; CHECK: dup {{v[0-9]+}}.4h, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4h, v0.h[2]
+; CHECK-NEXT: ret
%shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
ret <4 x i16> %shuffle
}
define <2 x i32> @test_vdup_lane_s32(<2 x i32> %v1) #0 {
; CHECK-LABEL: test_vdup_lane_s32:
-; CHECK: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.2s, v0.s[1]
+; CHECK-NEXT: ret
%shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i32> %shuffle
}
define <16 x i8> @test_vdupq_lane_s8(<8 x i8> %v1) #0 {
; CHECK-LABEL: test_vdupq_lane_s8:
-; CHECK: {{v[0-9]+}}.16b, {{v[0-9]+}}.b[5]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.16b, v0.b[5]
+; CHECK-NEXT: ret
%shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <16 x i8> %shuffle
}
define <8 x i16> @test_vdupq_lane_s16(<4 x i16> %v1) #0 {
; CHECK-LABEL: test_vdupq_lane_s16:
-; CHECK: {{v[0-9]+}}.8h, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.8h, v0.h[2]
+; CHECK-NEXT: ret
%shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
ret <8 x i16> %shuffle
}
define <4 x i32> @test_vdupq_lane_s32(<2 x i32> %v1) #0 {
; CHECK-LABEL: test_vdupq_lane_s32:
-; CHECK: {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4s, v0.s[1]
+; CHECK-NEXT: ret
%shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %shuffle
}
define <2 x i64> @test_vdupq_lane_s64(<1 x i64> %v1) #0 {
; CHECK-LABEL: test_vdupq_lane_s64:
-; CHECK: {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.2d, v0.d[0]
+; CHECK-NEXT: ret
%shuffle = shufflevector <1 x i64> %v1, <1 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %shuffle
}
define <8 x i8> @test_vdup_laneq_s8(<16 x i8> %v1) #0 {
; CHECK-LABEL: test_vdup_laneq_s8:
-; CHECK: dup {{v[0-9]+}}.8b, {{v[0-9]+}}.b[5]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.8b, v0.b[5]
+; CHECK-NEXT: ret
%shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <8 x i8> %shuffle
}
define <4 x i16> @test_vdup_laneq_s16(<8 x i16> %v1) #0 {
; CHECK-LABEL: test_vdup_laneq_s16:
-; CHECK: dup {{v[0-9]+}}.4h, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.4h, v0.h[2]
+; CHECK-NEXT: ret
%shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
ret <4 x i16> %shuffle
}
define <2 x i32> @test_vdup_laneq_s32(<4 x i32> %v1) #0 {
; CHECK-LABEL: test_vdup_laneq_s32:
-; CHECK: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.2s, v0.s[1]
+; CHECK-NEXT: ret
%shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i32> %shuffle
}
define <16 x i8> @test_vdupq_laneq_s8(<16 x i8> %v1) #0 {
; CHECK-LABEL: test_vdupq_laneq_s8:
-; CHECK: dup {{v[0-9]+}}.16b, {{v[0-9]+}}.b[5]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.16b, v0.b[5]
+; CHECK-NEXT: ret
%shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <16 x i8> %shuffle
}
define <8 x i16> @test_vdupq_laneq_s16(<8 x i16> %v1) #0 {
; CHECK-LABEL: test_vdupq_laneq_s16:
-; CHECK: {{v[0-9]+}}.8h, {{v[0-9]+}}.h[2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.8h, v0.h[2]
+; CHECK-NEXT: ret
%shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
ret <8 x i16> %shuffle
}
define <4 x i32> @test_vdupq_laneq_s32(<4 x i32> %v1) #0 {
; CHECK-LABEL: test_vdupq_laneq_s32:
-; CHECK: dup {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.4s, v0.s[1]
+; CHECK-NEXT: ret
%shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %shuffle
}
define <2 x i64> @test_vdupq_laneq_s64(<2 x i64> %v1) #0 {
; CHECK-LABEL: test_vdupq_laneq_s64:
-; CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.2d, v0.d[0]
+; CHECK-NEXT: ret
%shuffle = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %shuffle
}
define i64 @test_bitcastv8i8toi64(<8 x i8> %in) {
; CHECK-LABEL: test_bitcastv8i8toi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%res = bitcast <8 x i8> %in to i64
-; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
ret i64 %res
}
define i64 @test_bitcastv4i16toi64(<4 x i16> %in) {
; CHECK-LABEL: test_bitcastv4i16toi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%res = bitcast <4 x i16> %in to i64
-; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
ret i64 %res
}
define i64 @test_bitcastv2i32toi64(<2 x i32> %in) {
; CHECK-LABEL: test_bitcastv2i32toi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%res = bitcast <2 x i32> %in to i64
-; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
ret i64 %res
}
define i64 @test_bitcastv2f32toi64(<2 x float> %in) {
; CHECK-LABEL: test_bitcastv2f32toi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%res = bitcast <2 x float> %in to i64
-; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
ret i64 %res
}
define i64 @test_bitcastv1i64toi64(<1 x i64> %in) {
; CHECK-LABEL: test_bitcastv1i64toi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%res = bitcast <1 x i64> %in to i64
-; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
ret i64 %res
}
define i64 @test_bitcastv1f64toi64(<1 x double> %in) {
; CHECK-LABEL: test_bitcastv1f64toi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%res = bitcast <1 x double> %in to i64
-; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
ret i64 %res
}
define <8 x i8> @test_bitcasti64tov8i8(i64 %in) {
; CHECK-LABEL: test_bitcasti64tov8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%res = bitcast i64 %in to <8 x i8>
-; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <8 x i8> %res
}
define <4 x i16> @test_bitcasti64tov4i16(i64 %in) {
; CHECK-LABEL: test_bitcasti64tov4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%res = bitcast i64 %in to <4 x i16>
-; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <4 x i16> %res
}
define <2 x i32> @test_bitcasti64tov2i32(i64 %in) {
; CHECK-LABEL: test_bitcasti64tov2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%res = bitcast i64 %in to <2 x i32>
-; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <2 x i32> %res
}
define <2 x float> @test_bitcasti64tov2f32(i64 %in) {
; CHECK-LABEL: test_bitcasti64tov2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%res = bitcast i64 %in to <2 x float>
-; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <2 x float> %res
}
define <1 x i64> @test_bitcasti64tov1i64(i64 %in) {
; CHECK-LABEL: test_bitcasti64tov1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%res = bitcast i64 %in to <1 x i64>
-; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <1 x i64> %res
}
define <1 x double> @test_bitcasti64tov1f64(i64 %in) {
; CHECK-LABEL: test_bitcasti64tov1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%res = bitcast i64 %in to <1 x double>
-; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <1 x double> %res
}
define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {
; CHECK-LABEL: test_bitcastv8i8tov1f64:
-; CHECK: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: fcvtzs {{[xd][0-9]+}}, {{d[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v0.8b, v0.8b
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%sub.i = sub <8 x i8> zeroinitializer, %a
%1 = bitcast <8 x i8> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -701,8 +953,11 @@ define <1 x i64> @test_bitcastv8i8tov1f6
define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {
; CHECK-LABEL: test_bitcastv4i16tov1f64:
-; CHECK: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-; CHECK-NEXT: fcvtzs {{[dx][0-9]+}}, {{d[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v0.4h, v0.4h
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%sub.i = sub <4 x i16> zeroinitializer, %a
%1 = bitcast <4 x i16> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -711,8 +966,11 @@ define <1 x i64> @test_bitcastv4i16tov1f
define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 {
; CHECK-LABEL: test_bitcastv2i32tov1f64:
-; CHECK: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-; CHECK-NEXT: fcvtzs {{[xd][0-9]+}}, {{d[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v0.2s, v0.2s
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%sub.i = sub <2 x i32> zeroinitializer, %a
%1 = bitcast <2 x i32> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -721,8 +979,11 @@ define <1 x i64> @test_bitcastv2i32tov1f
define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1i64tov1f64:
-; CHECK: neg {{d[0-9]+}}, {{d[0-9]+}}
-; CHECK-NEXT: fcvtzs {{[dx][0-9]+}}, {{d[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg d0, d0
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%sub.i = sub <1 x i64> zeroinitializer, %a
%1 = bitcast <1 x i64> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -731,8 +992,11 @@ define <1 x i64> @test_bitcastv1i64tov1f
define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 {
; CHECK-LABEL: test_bitcastv2f32tov1f64:
-; CHECK: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-; CHECK-NEXT: fcvtzs {{[xd][0-9]+}}, {{d[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: fneg v0.2s, v0.2s
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a
%1 = bitcast <2 x float> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -741,8 +1005,12 @@ define <1 x i64> @test_bitcastv2f32tov1f
define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov8i8:
-; CHECK: scvtf {{d[0-9]+}}, {{[xd][0-9]+}}
-; CHECK-NEXT: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: scvtf d0, x8
+; CHECK-NEXT: neg v0.8b, v0.8b
+; CHECK-NEXT: ret
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <8 x i8>
%sub.i = sub <8 x i8> zeroinitializer, %1
@@ -751,8 +1019,12 @@ define <8 x i8> @test_bitcastv1f64tov8i8
define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov4i16:
-; CHECK: scvtf {{d[0-9]+}}, {{[xd][0-9]+}}
-; CHECK-NEXT: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: scvtf d0, x8
+; CHECK-NEXT: neg v0.4h, v0.4h
+; CHECK-NEXT: ret
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <4 x i16>
%sub.i = sub <4 x i16> zeroinitializer, %1
@@ -761,8 +1033,12 @@ define <4 x i16> @test_bitcastv1f64tov4i
define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov2i32:
-; CHECK: scvtf {{d[0-9]+}}, {{[xd][0-9]+}}
-; CHECK-NEXT: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: scvtf d0, x8
+; CHECK-NEXT: neg v0.2s, v0.2s
+; CHECK-NEXT: ret
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <2 x i32>
%sub.i = sub <2 x i32> zeroinitializer, %1
@@ -771,8 +1047,12 @@ define <2 x i32> @test_bitcastv1f64tov2i
define <1 x i64> @test_bitcastv1f64tov1i64(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov1i64:
-; CHECK: scvtf {{d[0-9]+}}, {{[xd][0-9]+}}
-; CHECK-NEXT: neg {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: scvtf d0, x8
+; CHECK-NEXT: neg d0, d0
+; CHECK-NEXT: ret
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <1 x i64>
%sub.i = sub <1 x i64> zeroinitializer, %1
@@ -781,8 +1061,12 @@ define <1 x i64> @test_bitcastv1f64tov1i
define <2 x float> @test_bitcastv1f64tov2f32(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov2f32:
-; CHECK: scvtf {{d[0-9]+}}, {{[xd][0-9]+}}
-; CHECK-NEXT: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: scvtf d0, x8
+; CHECK-NEXT: fneg v0.2s, v0.2s
+; CHECK-NEXT: ret
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <2 x float>
%sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %1
@@ -882,7 +1166,9 @@ define <4 x i32> @testDUP.v1i32(<1 x i32
define <8 x i8> @getl(<16 x i8> %x) #0 {
; CHECK-LABEL: getl:
-; CHECK: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%vecext = extractelement <16 x i8> %x, i32 0
%vecinit = insertelement <8 x i8> undef, i8 %vecext, i32 0
%vecext1 = extractelement <16 x i8> %x, i32 1
@@ -902,15 +1188,22 @@ define <8 x i8> @getl(<16 x i8> %x) #0 {
ret <8 x i8> %vecinit14
}
-; CHECK-LABEL: test_extracts_inserts_varidx_extract:
-; CHECK: str q0
-; CHECK-DAG: and [[MASKED_IDX:x[0-9]+]], x0, #0x7
-; CHECK: bfi [[PTR:x[0-9]+]], [[MASKED_IDX]], #1, #3
-; CHECK-DAG: ldr h[[R:[0-9]+]], {{\[}}[[PTR]]{{\]}}
-; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
-; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
-; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {
+; CHECK-LABEL: test_extracts_inserts_varidx_extract:
+; CHECK: // %bb.0:
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: str q0, [sp, #-16]!
+; CHECK-NEXT: and x8, x0, #0x7
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: bfi x9, x8, #1, #3
+; CHECK-NEXT: ldr h1, [x9]
+; CHECK-NEXT: mov v1.h[1], v0.h[1]
+; CHECK-NEXT: mov v1.h[2], v0.h[2]
+; CHECK-NEXT: mov v1.h[3], v0.h[3]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: add sp, sp, #16 // =16
+; CHECK-NEXT: ret
%tmp = extractelement <8 x i16> %x, i32 %idx
%tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0
%tmp3 = extractelement <8 x i16> %x, i32 1
@@ -922,15 +1215,23 @@ define <4 x i16> @test_extracts_inserts_
ret <4 x i16> %tmp8
}
-; CHECK-LABEL: test_extracts_inserts_varidx_insert:
-; CHECK: and [[MASKED_IDX:x[0-9]+]], x0, #0x3
-; CHECK: bfi x9, [[MASKED_IDX]], #1, #2
-; CHECK: str h0, [x9]
-; CHECK-DAG: ldr d[[R:[0-9]+]]
-; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
-; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
-; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
+; CHECK-LABEL: test_extracts_inserts_varidx_insert:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #16 // =16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: and x8, x0, #0x3
+; CHECK-NEXT: add x9, sp, #8 // =8
+; CHECK-NEXT: bfi x9, x8, #1, #2
+; CHECK-NEXT: str h0, [x9]
+; CHECK-NEXT: ldr d1, [sp, #8]
+; CHECK-NEXT: mov v1.h[1], v0.h[1]
+; CHECK-NEXT: mov v1.h[2], v0.h[2]
+; CHECK-NEXT: mov v1.h[3], v0.h[3]
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: add sp, sp, #16 // =16
+; CHECK-NEXT: ret
%tmp = extractelement <8 x i16> %x, i32 0
%tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx
%tmp3 = extractelement <8 x i16> %x, i32 1
@@ -944,7 +1245,10 @@ define <4 x i16> @test_extracts_inserts_
define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) {
; CHECK-LABEL: test_dup_v2i32_v4i16:
-; CHECK: dup v0.4h, v0.h[2]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4h, v0.h[2]
+; CHECK-NEXT: ret
entry:
%x = extractelement <2 x i32> %a, i32 1
%vget_lane = trunc i32 %x to i16
@@ -957,7 +1261,9 @@ entry:
define <8 x i16> @test_dup_v4i32_v8i16(<4 x i32> %a) {
; CHECK-LABEL: test_dup_v4i32_v8i16:
-; CHECK: dup v0.8h, v0.h[6]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.8h, v0.h[6]
+; CHECK-NEXT: ret
entry:
%x = extractelement <4 x i32> %a, i32 3
%vget_lane = trunc i32 %x to i16
@@ -974,7 +1280,10 @@ entry:
define <4 x i16> @test_dup_v1i64_v4i16(<1 x i64> %a) {
; CHECK-LABEL: test_dup_v1i64_v4i16:
-; CHECK: dup v0.4h, v0.h[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4h, v0.h[0]
+; CHECK-NEXT: ret
entry:
%x = extractelement <1 x i64> %a, i32 0
%vget_lane = trunc i64 %x to i16
@@ -987,7 +1296,10 @@ entry:
define <2 x i32> @test_dup_v1i64_v2i32(<1 x i64> %a) {
; CHECK-LABEL: test_dup_v1i64_v2i32:
-; CHECK: dup v0.2s, v0.s[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: ret
entry:
%x = extractelement <1 x i64> %a, i32 0
%vget_lane = trunc i64 %x to i32
@@ -998,7 +1310,9 @@ entry:
define <8 x i16> @test_dup_v2i64_v8i16(<2 x i64> %a) {
; CHECK-LABEL: test_dup_v2i64_v8i16:
-; CHECK: dup v0.8h, v0.h[4]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.8h, v0.h[4]
+; CHECK-NEXT: ret
entry:
%x = extractelement <2 x i64> %a, i32 1
%vget_lane = trunc i64 %x to i16
@@ -1015,7 +1329,9 @@ entry:
define <4 x i32> @test_dup_v2i64_v4i32(<2 x i64> %a) {
; CHECK-LABEL: test_dup_v2i64_v4i32:
-; CHECK: dup v0.4s, v0.s[2]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.4s, v0.s[2]
+; CHECK-NEXT: ret
entry:
%x = extractelement <2 x i64> %a, i32 1
%vget_lane = trunc i64 %x to i32
@@ -1028,7 +1344,9 @@ entry:
define <4 x i16> @test_dup_v4i32_v4i16(<4 x i32> %a) {
; CHECK-LABEL: test_dup_v4i32_v4i16:
-; CHECK: dup v0.4h, v0.h[2]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.4h, v0.h[2]
+; CHECK-NEXT: ret
entry:
%x = extractelement <4 x i32> %a, i32 1
%vget_lane = trunc i32 %x to i16
@@ -1041,7 +1359,9 @@ entry:
define <4 x i16> @test_dup_v2i64_v4i16(<2 x i64> %a) {
; CHECK-LABEL: test_dup_v2i64_v4i16:
-; CHECK: dup v0.4h, v0.h[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.4h, v0.h[0]
+; CHECK-NEXT: ret
entry:
%x = extractelement <2 x i64> %a, i32 0
%vget_lane = trunc i64 %x to i16
@@ -1054,7 +1374,9 @@ entry:
define <2 x i32> @test_dup_v2i64_v2i32(<2 x i64> %a) {
; CHECK-LABEL: test_dup_v2i64_v2i32:
-; CHECK: dup v0.2s, v0.s[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: ret
entry:
%x = extractelement <2 x i64> %a, i32 0
%vget_lane = trunc i64 %x to i32
@@ -1066,8 +1388,9 @@ entry:
define <2 x float> @test_scalar_to_vector_f32_to_v2f32(<2 x float> %a) {
; CHECK-LABEL: test_scalar_to_vector_f32_to_v2f32:
-; CHECK: fmaxp s{{[0-9]+}}, v{{[0-9]+}}.2s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmaxp s0, v0.2s
+; CHECK-NEXT: ret
entry:
%0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)
%1 = insertelement <1 x float> undef, float %0, i32 0
@@ -1078,8 +1401,9 @@ entry:
define <4 x float> @test_scalar_to_vector_f32_to_v4f32(<2 x float> %a) {
; CHECK-LABEL: test_scalar_to_vector_f32_to_v4f32:
-; CHECK: fmaxp s{{[0-9]+}}, v{{[0-9]+}}.2s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmaxp s0, v0.2s
+; CHECK-NEXT: ret
entry:
%0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)
%1 = insertelement <1 x float> undef, float %0, i32 0
@@ -1092,7 +1416,10 @@ declare float @llvm.aarch64.neon.fmaxv.f
define <2 x i32> @test_concat_undef_v1i32(<2 x i32> %a) {
; CHECK-LABEL: test_concat_undef_v1i32:
-; CHECK: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: ret
entry:
%0 = extractelement <2 x i32> %a, i32 0
%vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 1
@@ -1103,8 +1430,10 @@ declare i32 @llvm.aarch64.neon.sqabs.i32
define <2 x i32> @test_concat_v1i32_undef(i32 %a) {
; CHECK-LABEL: test_concat_v1i32_undef:
-; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: sqabs s0, s0
+; CHECK-NEXT: ret
entry:
%b = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)
%vecinit.i432 = insertelement <2 x i32> undef, i32 %b, i32 0
@@ -1113,7 +1442,10 @@ entry:
define <2 x i32> @test_concat_same_v1i32_v1i32(<2 x i32> %a) {
; CHECK-LABEL: test_concat_same_v1i32_v1i32:
-; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: ret
entry:
%0 = extractelement <2 x i32> %a, i32 0
%vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 0
@@ -1123,9 +1455,15 @@ entry:
define <2 x i32> @test_concat_diff_v1i32_v1i32(i32 %a, i32 %b) {
; CHECK-LABEL: test_concat_diff_v1i32_v1i32:
-; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
-; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
-; CHECK: mov {{v[0-9]+}}.s[1], w{{[0-9]+}}
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: sqabs s1, s1
+; CHECK-NEXT: sqabs s0, s0
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)
%d = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -1137,7 +1475,9 @@ entry:
define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {
; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
ret <16 x i8> %vecinit30
@@ -1145,7 +1485,10 @@ entry:
define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <8 x i8> %x, i32 0
%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
@@ -1169,7 +1512,10 @@ entry:
define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <16 x i8> %x, i32 0
%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
@@ -1208,7 +1554,11 @@ entry:
define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <8 x i8> %x, i32 0
%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
@@ -1247,7 +1597,9 @@ entry:
define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {
; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
ret <8 x i16> %vecinit14
@@ -1255,7 +1607,10 @@ entry:
define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <4 x i16> %x, i32 0
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
@@ -1271,7 +1626,10 @@ entry:
define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <8 x i16> %x, i32 0
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
@@ -1294,7 +1652,11 @@ entry:
define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <4 x i16> %x, i32 0
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
@@ -1317,7 +1679,9 @@ entry:
define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {
; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x i32> %vecinit6
@@ -1325,7 +1689,10 @@ entry:
define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <2 x i32> %x, i32 0
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -1337,7 +1704,10 @@ entry:
define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <4 x i32> %x, i32 0
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -1352,7 +1722,11 @@ entry:
define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {
; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i32> %vecinit6
@@ -1360,7 +1734,9 @@ entry:
define <2 x i64> @test_concat_v2i64_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) #0 {
; CHECK-LABEL: test_concat_v2i64_v2i64_v2i64:
-; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
entry:
%vecinit2 = shufflevector <2 x i64> %x, <2 x i64> %y, <2 x i32> <i32 0, i32 2>
ret <2 x i64> %vecinit2
@@ -1368,7 +1744,10 @@ entry:
define <2 x i64> @test_concat_v2i64_v1i64_v2i64(<1 x i64> %x, <2 x i64> %y) #0 {
; CHECK-LABEL: test_concat_v2i64_v1i64_v2i64:
-; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <1 x i64> %x, i32 0
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
@@ -1378,7 +1757,10 @@ entry:
define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {
; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:
-; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <2 x i64> %x, i32 0
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
@@ -1389,7 +1771,11 @@ entry:
define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {
; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecext = extractelement <1 x i64> %x, i32 0
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
@@ -1401,84 +1787,113 @@ entry:
define <4 x i16> @concat_vector_v4i16_const() {
; CHECK-LABEL: concat_vector_v4i16_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
%r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %r
}
define <4 x i16> @concat_vector_v4i16_const_one() {
; CHECK-LABEL: concat_vector_v4i16_const_one:
-; CHECK: movi {{v[0-9]+}}.4h, #1
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.4h, #1
+; CHECK-NEXT: ret
%r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %r
}
define <4 x i32> @concat_vector_v4i32_const() {
; CHECK-LABEL: concat_vector_v4i32_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
%r = shufflevector <1 x i32> zeroinitializer, <1 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %r
}
define <8 x i8> @concat_vector_v8i8_const() {
; CHECK-LABEL: concat_vector_v8i8_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
%r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <8 x i32> zeroinitializer
ret <8 x i8> %r
}
define <8 x i16> @concat_vector_v8i16_const() {
; CHECK-LABEL: concat_vector_v8i16_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
%r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %r
}
define <8 x i16> @concat_vector_v8i16_const_one() {
; CHECK-LABEL: concat_vector_v8i16_const_one:
-; CHECK: movi {{v[0-9]+}}.8h, #1
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.8h, #1
+; CHECK-NEXT: ret
%r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %r
}
define <16 x i8> @concat_vector_v16i8_const() {
; CHECK-LABEL: concat_vector_v16i8_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
%r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <16 x i32> zeroinitializer
ret <16 x i8> %r
}
define <4 x i16> @concat_vector_v4i16(<1 x i16> %a) {
; CHECK-LABEL: concat_vector_v4i16:
-; CHECK: dup v0.4h, v0.h[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4h, v0.h[0]
+; CHECK-NEXT: ret
%r = shufflevector <1 x i16> %a, <1 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %r
}
define <4 x i32> @concat_vector_v4i32(<1 x i32> %a) {
; CHECK-LABEL: concat_vector_v4i32:
-; CHECK: dup v0.4s, v0.s[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4s, v0.s[0]
+; CHECK-NEXT: ret
%r = shufflevector <1 x i32> %a, <1 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %r
}
define <8 x i8> @concat_vector_v8i8(<1 x i8> %a) {
; CHECK-LABEL: concat_vector_v8i8:
-; CHECK: dup v0.8b, v0.b[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.8b, v0.b[0]
+; CHECK-NEXT: ret
%r = shufflevector <1 x i8> %a, <1 x i8> undef, <8 x i32> zeroinitializer
ret <8 x i8> %r
}
define <8 x i16> @concat_vector_v8i16(<1 x i16> %a) {
; CHECK-LABEL: concat_vector_v8i16:
-; CHECK: dup v0.8h, v0.h[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.8h, v0.h[0]
+; CHECK-NEXT: ret
%r = shufflevector <1 x i16> %a, <1 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %r
}
define <16 x i8> @concat_vector_v16i8(<1 x i8> %a) {
; CHECK-LABEL: concat_vector_v16i8:
-; CHECK: dup v0.16b, v0.b[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.16b, v0.b[0]
+; CHECK-NEXT: ret
%r = shufflevector <1 x i8> %a, <1 x i8> undef, <16 x i32> zeroinitializer
ret <16 x i8> %r
}
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